View MC68HC912B32CFU8_181266.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this document by MC68HC912B32TS/D
MC68HC912B32
Technical Summary
16-Bit Microcontroller
1 Introduction
The MC68HC912B32 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 32-Kbyte flash EEPROM, 1-Kbyte RAM, 768-byte EEPROM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel timer and 16-bit pulse accumulator, an 8-bit analog-to-digital converter (ADC), a four-channel pulse-width modulator (PWM), and a J1850-compatible byte data link communications module (BDLC). The chip is the first 16-bit microcontroller to include both byte-erasable EEPROM and flash EEPROM on the same device. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the Lite integration module (LIM). The MC68HC912B32 has full 16-bit data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. 1.1 Features * 16-Bit CPU12 -- Upward Compatible with M68HC11 Instruction Set -- Interrupt Stacking and Programmer's Model Identical to M68HC11 -- 20-Bit ALU -- Instruction Queue -- Enhanced Indexed Addressing -- Fuzzy Logic Instructions * Multiplexed Bus -- Single Chip or Expanded -- 16/16 Wide or 16/8 Narrow Modes * Memory -- 32-Kbyte Flash EEPROM with 2-Kbyte Erase-Protected Boot Block -- 768-B yte EEPROM -- 1-Kbyte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write * 8-Channel, 8-Bit Analog-to-Digital Converter * 8-Channel Timer -- Each Channel Fully Configurable as Either Input Capture or Output Compare -- Simple PWM Mode -- Modulo Reset of Timer Counter * 16-Bit Pulse Accumulator -- External Event Counting -- Gated Time Accumulation * Pulse-Width Modulator -- 8-Bit, 4-Channel or 16-Bit, 2-Channel -- Separate Control for Each Pulse Width and Duty Cycle
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) MOTOROLA INC., 1997
M
-- Programmable Center-Aligned or Left-Aligned Outputs * Serial Interfaces -- Asynchronous Serial Communications Interface (SCI) -- Synchronous Serial Peripheral Interface (SPI) -- J1850 Byte Data Link Communication (BDLC) * COP Watchdog Timer, Clock Monitor, and Periodic Interrupt Timer * 80-Pin QFP Package -- Up to 63 General-Purpose I/O Lines -- 2.7V-5.5V Operation at 8 MHz * Single-Wire Background DebugTM Mode (BDM) * On-Chip Hardware Breakpoints 1.2 Ordering Information The MC68HC912B32 is packaged in 80-pin quad flat pack (QFP) packaging and is shipped in two-piece sample packs, 50-piece trays, or 250-piece bricks. Operating temperature range and voltage requirements are specified when ordering the MC68HC912B32 device. Refer to Table 1 for part numbers. Table 1 MC68HC912B32 Device Ordering Information
Order Number MC68HC912B32FU8 MC68HC912B32CFU8 Temperature Range 0 to +70 C -40 to +85 C Designator -- C V M -- C -- 2.7V-3.6V 2.7V-5.5V 4.5V-5.5V 8 MHz 80-Pin QFP Single Tray 50 Pcs Voltage Frequency Package
MC68HC912B32VFU8 -40 to +105 C MC68HC912B32MFU8 -40 to +125 C MC68C912B32FU8 MC68C912B32CFU8 MC68B912B32FU8 0 to +70 C -40 to +85 C 0 to +70 C
NOTE: This part is also available in 2-piece sample packs and 250-piece bricks.
Evaluation boards, assemblers, compilers, and debuggers are available from Motorola and from thirdparty suppliers. An up-to-date list of products that support the M68HC12 family of microcontrollers can be found on the World Wide Web at the following URL: http://www.mcu.motsps.com Documents to assist in product selection are available from the Motorola Literature Distribution Center or your local Motorola Sales Office: AMCU Device Selection Guide (SG166/D) AMCU Software and Development Tool Selector Guide (SG176/D)
MOTOROLA 2
MC68HC912B32 MC68HC912B32TS/D
TABLE OF CONTENTS
Section Page
1
1.1 1.2 1.3
Introduction
1 Features ......................................................................................................................................1 Ordering Information ...................................................................................................................2 MC68HC912B32 Block Diagram .................................................................................................5
2
2.1 2.2 2.3 2.4 2.5
3
3.1 3.2 3.3 3.4 3.5
4 5
5.1 5.2 5.3 5.4
6
6.1 6.2
7
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10
8
8.1 8.2
9
9.1 9.2 9.3 9.4 9.5 9.6
10
10.1 10.2 10.3 10.4 10.5 10.6
6 Programming Model ....................................................................................................................6 Data Types ..................................................................................................................................7 Addressing Modes .......................................................................................................................7 Indexed Addressing Modes .........................................................................................................8 Opcodes and Operands ..............................................................................................................8 Pinout and Signal Descriptions 9 MC68HC912B32 Pin Assignments .............................................................................................9 Power Supply Pins ....................................................................................................................10 Signal Descriptions ....................................................................................................................11 Port Signals ...............................................................................................................................15 Port Pull-Up, Pull-Down and Reduced Drive .............................................................................19 Register Block 20 Operating Modes and Resource Mapping 25 Operating Modes .......................................................................................................................25 Background Debug Mode ..........................................................................................................26 Internal Resource Mapping .......................................................................................................28 Memory Maps ............................................................................................................................31 Bus Control and Input/Output 32 Detecting Access Type from External Signals ..........................................................................32 Registers ...................................................................................................................................32 Flash EEPROM 37 Overview ...................................................................................................................................37 Flash EEPROM Control Block ...................................................................................................37 Flash EEPROM Array ...............................................................................................................37 Flash EEPROM Registers .........................................................................................................37 Operation ...................................................................................................................................40 Programming the Flash EEPROM ............................................................................................42 Erasing the Flash EEPROM ......................................................................................................44 Program/Erase Protection Interlocks .........................................................................................46 Stop or Wait Mode .....................................................................................................................46 Test Mode .................................................................................................................................46 EEPROM 47 EEPROM Programmer's Model ................................................................................................47 EEPROM Control Registers ......................................................................................................48 Resets and Interrupts 52 Exception Priority ......................................................................................................................52 Maskable Interrupts ...................................................................................................................52 Interrupt Control and Priority Registers .....................................................................................53 Resets .......................................................................................................................................54 Effects of Reset .........................................................................................................................54 Register Stacking ......................................................................................................................55 Clock Functions 57 Clock Sources ...........................................................................................................................57 Computer Operating Properly (COP) ........................................................................................57 Real-Time Interrupt ...................................................................................................................57 Clock Monitor ............................................................................................................................57 Clock Function Registers ..........................................................................................................58 Clock Divider Chains .................................................................................................................60
Central Processing Unit
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 3
TABLE OF CONTENTS (Continued)
Section Page 63 PWM Register Description ........................................................................................................65 PWM Boundary Cases ..............................................................................................................72 Standard Timer Module 73 Timer Registers .........................................................................................................................74 Timer Operation in Modes .........................................................................................................82 Serial Interface 83 Block Diagram ...........................................................................................................................83 Serial Communication Interface (SCI) .......................................................................................83 Serial Peripheral Interface (SPI) ................................................................................................90 Port S ........................................................................................................................................96 Byte Data Link Communications Module (BDLC) 98 Features ....................................................................................................................................98 BDLC Operating Modes ............................................................................................................98 Loopback Modes .......................................................................................................................99 BDLC Registers .........................................................................................................................99 J1850 Bus Errors .....................................................................................................................106 Analog-To-Digital Converter 108 Functional Description .............................................................................................................108 ATD Registers .........................................................................................................................108 ATD Mode Operation ..............................................................................................................114 Development Support 115 Instruction Queue ....................................................................................................................115 Background Debug Mode ........................................................................................................115 Breakpoints .............................................................................................................................123 Instruction Tagging ..................................................................................................................127
11
11.1 11.2
Pulse-Width Modulator
12
12.1 12.2
13
13.1 13.2 13.3 13.4
14
14.1 14.2 14.3 14.4 14.5
15
15.1 15.2 15.3
16
16.1 16.2 16.3 16.4
MOTOROLA 4
MC68HC912B32 MC68HC912B32TS/D
1.3 MC68HC912B32 Block Diagram
VFP
32-KBYTE FLASH EEPROM 1-KBYTE RAM 768-BYTE EEPROM CPU12 ATD CONVERTER
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
VRH VRL VDDA VSSA
VRH VRL VDDA VSSA PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PDLC0 PDLC1
BKGD
SMODN / TAGHI
PERIODIC INTERRUPT COP WATCHDOG CLOCK MONITOR BREAK POINTS
SPI
SDI/MISO SDO/MOSI SCK CS/SS PW0 PW1 PW2 PW3 I/O I/O I/O I/O DLCRx DLCTx
MULTIPLEXED ADDRESS/DATA BUS PWM DDRA PORT A DDRB PORT B I/O
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
BDLC
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
PORT DLC
DDRDLC
PORT P
DDRP
PORT S
DDRS
EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7
XIRQ IRQ/VPP R/W LSTRB / TAGLO ECLK IPIPE0 / MODA IPIPE1 / MODB DBE
PORT E
LITE INTEGRATION MODULE (LIM)
SCI I/O
RxD TxD I/O I/O
PORT T
SINGLE-WIRE BACKGROUND DEBUG MODULE
IOC0 IOC1 IOC2 TIMER AND IOC3 OC7 IOC4 PULSE ACCUMULATOR IOC5 IOC6 PAI
DDRT
PORT AD
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
WIDE BUS
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
I/O
I/O I/O I/O I/O I/O
PDLC2 PDLC3 PDLC4 PDLC5 PDLC6
NARROW BUS
VDD x 2 VSS x 2
POWER FOR INTERNAL CIRCUITRY
VDDX x 2 VSSX x 2
POWER FOR I/O DRIVERS
Figure 1 MC68HC912B32 Block Diagram
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 5
2 Central Processing Unit
The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The CPU12 allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space. An instruction queue buffers program information so the CPU always has immediate access to at least three bytes of machine code at the start of every instruction. The CPU12 also offers an extensive set of indexed addressing capabilities. 2.1 Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. 7 15 A 07 D B 0 0 8-BIT ACCUMULATORS A & B
OR
16-BIT DOUBLE ACCUMULATOR D
15
IX
0
INDEX REGISTER X
15
IY
0
INDEX REGISTER Y
15
SP
0
STACK POINTER
15
PC
0
PROGRAM COUNTER
SXHINZVC
CONDITION CODE REGISTER
HC12 PROG MODEL
Figure 2 Programming Model Accumulators A and B are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8bit accumulators as a 16-bit double accumulator (accumulator D). Index registers X and Y are used for indexed addressing mode. In the indexed addressing mode, the contents of a 16-bit index register are added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator to form the effective address of the operand to be used in the instruction. Stack pointer (SP) points to the last stack location used. The CPU12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts, and can also be used for temporary storage of data. The stack pointer can also be used in all indexed addressing modes. Program counter is a 16-bit register that holds the address of the next instruction to be executed. The program counter can be used in all indexed addressing modes except auto-increment/decrement. Condition Code Register (CCR) contains five status indicators, two interrupt masking bits, and a STOP disable bit. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a previous operation.
MOTOROLA 6
MC68HC912B32 MC68HC912B32TS/D
2.2 Data Types The CPU12 supports the following data types: * Bit data * 8-bit and 16-bit signed and unsigned integers * 16-bit unsigned fractions * 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. There are no special requirements for alignment of instructions or operands. 2.3 Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 2 is a summary of the available addressing modes. Table 2 M68HC12 Addressing Mode Summary
Addressing Mode Inherent Source Format INST (no externally supplied operands) INST #opr8i or INST #opr16i INST opr8a INST opr16a INST rel8 or INST rel16 INST oprx5,xysp INST oprx3,-xys INST oprx3,+xys INST oprx3,xys- INST oprx3,xys+ INST abd,xysp INST oprx9,xysp INST oprx16,xysp INST [oprx16,xysp] Abbreviation INH Description Operands (if any) are in CPU registers Operand is included in instruction stream 8- or 16-bit size implied by context Operand is the lower 8-bits of an address in the range $0000 - $00FF Operand is a 16-bit address An 8-bit or 16-bit relative offset from the current pc is supplied in the instruction 5-bit signed constant offset from x, y, sp, or pc Auto pre-decrement x, y, or sp by 1 ~ 8 Auto pre-increment x, y, or sp by 1 ~ 8 Auto post-decrement x, y, or sp by 1 ~ 8 Auto post-increment x, y, or sp by 1 ~ 8 Indexed with 8-bit (A or B) or 16-bit (D) accumulator offset from x, y, sp, or pc 9-bit signed constant offset from x, y, sp, or pc (lower 8-bits of offset in one extension byte) 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) Pointer to operand is found at... 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) Pointer to operand is found at... x, y, sp, or pc plus the value in D
Immediate Direct Extended Relative Indexed (5-bit offset) Indexed (auto pre-decrement) Indexed (auto pre-increment) Indexed (auto postdecrement) Indexed (auto post-increment) Indexed (accumulator offset) Indexed (9-bit offset) Indexed (16-bit offset) Indexed-Indirect (16-bit offset) Indexed-Indirect (D accumulator offset)
IMM DIR EXT REL IDX IDX IDX IDX IDX IDX IDX1 IDX2 [IDX2]
INST [D,xysp]
[D,IDX]
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 7
2.4 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The postbyte and extensions do the following tasks: * Specify which index register is used * Determine whether a value in an accumulator is used as an offset * Enable automatic pre- or post-increment or decrement * Specify use of 5-bit, 9-bit, or 16-bit signed offsets Table 3 Summary of Indexed Operations
Postbyte Code (xb) Source Code Syntax Comments rr; 00 = X, 01 = Y, 10 = SP, 11 = PC 5-bit constant offset n = -16 to +15 r can specify X, Y, SP, or PC Constant offset (9- or 16-bit signed) z- 0 = 9-bit with sign in LSB of postbyte(s) 1 = 16-bit if z = s = 1, 16-bit offset indexed-indirect (see below) r can specify X, Y, SP, or PC 16-bit offset indexed-indirect rr can specify X, Y, SP, or PC
rr0nnnnn
,r n,r -n,r n,r -n,r
111rr0zs
-256 < n < 255 0 < n < 65,535
111rr011 rr1pnnnn
[n,r] n,-r n,+r n,r- n,r+
0 < n < 65,535
Auto pre-decrement/increment or Auto post-decrement/increment; p = pre-(0) or post-(1), n = -8 to -1, +1 to +8 r can specify X, Y, or SP (PC not a valid choice) +8 = 0111 ... +1 = 0000 -1 = 1111 ... -8 = 1000 Accumulator offset (unsigned 8-bit or 16-bit) aa- 00 = A 01 = B 10 = D (16-bit) 11 = see accumulator D offset indexed-indirect r can specify X, Y, SP, or PC Accumulator D offset indexed-indirect r can specify X, Y, SP, or PC
111rr1aa
A,r B,r D,r
111rr111
[D,r]
2.5 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the opcode map. Opcodes on the second page are preceded by an additional byte with the value $18. To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop primitives. Extension bytes contain additional program information such as addresses, offsets, and immediate data.
MOTOROLA 8
MC68HC912B32 MC68HC912B32TS/D
3 Pinout and Signal Descriptions
3.1 MC68HC912B32 Pin Assignments The MC68HC912B32 is available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the 3.3 Signal Descriptions. Figure 3 shows pin assignments. Shaded pins are power and ground.
PORT DLC
PDLC0 / DLCRx PDLC1 / DLCTx PS7 / CS/SS PS6 / SCK
PORT S
PS5 / SDO/MOSI PS4 / SDI/MISO
PDLC2
PDLC3
PDLC4
PDLC5
PDLC6
PORT P
VDDX PP6 PP7 VSSX
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PS0 / RxD
PS1 / TxD
PS3
PS2
VFP
PP5 PP4 PW3 / PP3 PW2 / PP2 PW1/ PP1 PW0/ PP0 IOC0 / PT0 IOC1 / PT1 IOC2 / PT2 VDD VSS IOC3 / PT3 IOC4 / PT4 IOC5 / PT5 IOC6 / PT6 PAI / IOC7 / PT7 SMODN / TAGHI/ BKGD ADDR0 / DATA0 / PB0 ADDR1 / DATA1 / PB1 ADDR2 / DATA2 / PB2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 20
60 59 58 57 56 55 54 53 52
VSSA VDDA PAD7 / AN7 PAD6 / AN6 PAD4 / AN4 PAD3 / AN3 PAD2 / AN2 PAD1 / AN1 PAD0 / AN0 VRL VRH VSS VDD PA7 / DATA15 / ADDR15 PA6 / DATA14 / ADDR14 PA5 / DATA13 / ADDR13 PA4 / DATA12 / ADDR12 PA3 / DATA11 / ADDR11 PA2 / DATA10 / ADDR10 PAD5 / AN5
PORT T
MC68HC912B32 80-PIN QFP
51 50 49 48 47 46 45 44 43 42 41
PORT T
R/W / PE2
ECLK / PE4
MODB / IPIPE1 / PE6
MODA / IPIPE0 / PE5
LSTRB / TAGLO / PE3
IRQ/VPP / PE1
XIRQ / PE0
DBE / PE7
VDDX
RESET
EXTAL
XTAL
VSSX
ADDR8 / DATA8 / PA0
ADDR3 / DATA3 / PB3
ADDR4 / DATA4 / PB4
ADDR5 / DATA5 / PB5
ADDR6 / DATA6 / PB6
PORT B
ADDR7 / DATA7 / PB7
ADDR9 / DATA9 / PA1
PORT A*
HC12 80QFP
PORT E
PORT E
* In narrow mode, high and low data bytes are multiplexed in alternate bus cycles on port A.
Figure 3 Pin Assignments for MC68HC912B32
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 9
PORT AD
3.2 Power Supply Pins MC68HC912B32 power and ground pins are described below and summarized in Table 4. 3.2.1 Internal Power (VDD) and Ground (VSS) Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, shortduration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. 3.2.2 External Power (VDDX) and Ground (VSSX) External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. 3.2.3 VDDA, VSSA Provides operating voltage and ground for the analog-to-digital converter. This allows the supply voltage to the A/D to be bypassed independently. 3.2.4 Analog-to-Digital Reference Voltages (VRH, VRL) 3.2.5 VFP Flash EEPROM programming voltage and supply voltage during normal operation. 3.2.6 VPP High voltage supply to EEPROM. Used to monitor charge pump output and testing. Not intended for general applications use. Table 4 MC68HC912B32 Power and Ground Connection Summary
Mnemonic VDD VSS VDDX VSSX VDDA VSSA VRH VRL VFP VPP Pin Number 10, 47 Internal power and ground. 11, 48 31, 78 30, 77 59 60 49 50 69 37 Reference voltages for the analog-to-digital converter. Programming voltage for the Flash EEPROM and required supply for normal operation. High voltage supply to EEPROM used for test purposes only in special modes. Operating voltage and ground for the analog-to-digital converter, allows the supply voltage to the A/D to be bypassed independently. External power and ground, supply to pin drivers. Description
MOTOROLA 10
MC68HC912B32 MC68HC912B32TS/D
3.3 Signal Descriptions 3.3.1 Crystal Driver and External Clock Input (XTAL, EXTAL) These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. Out of reset the frequency applied to EXTAL is twice the desired E-clock rate. All the device clocks are derived from the EXTAL input frequency.
C EXTAL
MCU
XTAL
10 M
2xE CRYSTAL C
COMMON XTAL CONN
Figure 4 Common Crystal Connections
EXTAL
2xE CMOS-COMPATIBLE EXTERNAL OSCILLATOR
MCU
XTAL NC
EXT EXTAL CONN
Figure 5 External Oscillator Connections XTAL is the crystal output. The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal. The XTAL output can be buffered with a high-impedance buffer to drive the EXTAL input of another device. In all cases take extra care in the circuit board layout around the oscillator pins. Load capacitances shown in the oscillator circuits include all stray layout capacitances. Refer to Figure 4 and Figure 5 for diagrams of oscillator circuits. 3.3.2 E-Clock Output (ECLK) ECLK is the output connection for the internal bus clock and is used to demultiplex the address and data and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency out of reset. Eclock output can be turned off in single-chip modes to reduce the effects of RFI. In special peripheral mode the E clock is an input to the MCU. All clocks, including the E-clock, are halted when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 11
3.3.3 Reset (RESET) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously. This allows the part to reach a proper reset state even if the clocks have failed, while allowing synchronized operation when starting out of reset. It is possible to determine whether a reset was caused by an internal source or an external source. An internal source drives the pin low for 16 cycles; eight cycles later the pin is sampled. If the pin has returned high, either the COP watchdog vector or clock monitor vector will be taken. If the pin is still low, the external reset is determined to be active and the reset vector is taken. Hold reset low for at least 32 cycles to assure that the reset vector is taken in the event that an internal COP watchdog time-out or clock monitor fail occurs. 3.3.4 Maskable Interrupt Request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always configured to level-sensitive triggering at reset. When the MCU is reset the IRQ function is masked in the condition code register. This pin is always an input and can always be read. In special modes it can be used to apply external EEPROM VPP in support of EEPROM testing. External VPP is not needed for normal EEPROM program and erase cycles. Because the IRQ pin is also used as an EEPROM programming voltage pin, there is an internal resistive pull-up on the pin. 3.3.5 Nonmaskable Interrupt (XIRQ) The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPE in the PUCR register. XIRQ is often used as a power loss detect interrupt. Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be configured for level-sensitive operation if there is more than one source of IRQ interrupt), each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request. If the interrupt line is held low, the MCU will recognize another interrupt as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an interrupt). 3.3.6 Mode Select (SMODN, MODA, and MODB) The state of these pins during reset determine the MCU operating mode. After reset, MODA and MODB can be configured as instruction queue tracking signals IPIPE0 and IPIPE1. MODA and MODB have active pulldowns during reset. The SMODN pin can be used as BKGD or TAGHI after reset. 3.3.7 Single-Wire Background Mode Pin (BKGD) The BKGD pin receives and transmits serial background debugging commands. A special self-timing protocol is used. The BKGD pin has an active pull-up when configured as input; BKGD has no pull-up control. Refer to 16 Development Support.
MOTOROLA 12
MC68HC912B32 MC68HC912B32TS/D
3.3.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0]) External bus pins share function with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses. In expanded wide mode, ports A and B are used for multiplexed 16-bit data and address buses. PA[7:0] correspond to ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0]. In expanded narrow mode, ports A and B are used for the 16-bit address bus, and an 8-bit data bus is multiplexed with the most significant half of the address bus on port A. In this mode, 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or DATA[7:0], depending on the bus cycle. The state of the address pin should be latched at the rising edge of E. To allow for maximum address setup time at external devices, a transparent latch should be used. 3.3.9 Read/Write (R/W) In all modes this pin can be used as I/O and is a general-purpose input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. 3.3.10 Low-Byte Strobe (LSTRB) In all modes this pin can be used as I/O and is a general-purpose input with an active pull-up out of reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register. This signal is used in write operations and so external low byte writes will not be possible until this function is enabled. This pin is also used as TAGLO in special expanded modes and is multiplexed with the LSTRB function. 3.3.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0) These signals are used to track the state of the internal instruction execution queue. Execution state is time-multiplexed on the two signals. Refer to 16 Development Support. 3.3.12 Data Bus Enable (DBE) The DBE pin (PE7) is an active low signal that will be asserted low during E-clock high time. DBE provides separation between output of a multiplexed address and the input of data. When an external address is stretched, DBE is asserted during what would be the last quarter cycle of the last E-clock cycle of stretch. In expanded modes this pin is used to enable the drive control of external buses during external reads. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled out of reset in expanded modes. This pin has an active pull-up during and after reset in single-chip modes.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 13
Table 5 MC68HC912B32 Signal Description Summary
Pin Name PW[3:0] ADDR[7:0] DATA[7:0] ADDR[15:8] DATA[15:8] IOC[7:0] PAI AN[7:0] DBE MODB, MODA IPIPE1, IPIPE0 ECLK Pin Number 3-6 25-18 46-39 16-12, 9-7 16 58-51 26 27, 28 27, 28 29 Description Pulse Width Modulator channel outputs. External bus pins share function with general-purpose I/O ports A and B. In single chip modes, the pins can be used for I/O. In expanded modes, the pins are used for the external buses. Pins used for input capture and output compare in the timer and pulse accumulator subsystem. Pulse accumulator input Analog inputs for the analog-to-digital conversion module Data bus control and, in expanded mode, enables the drive control of external buses during external reads. State of mode select pins during reset determine the initial operating mode of the MCU. After reset, MODB and MODA can be configured as instruction queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins. E-clock is the output connection for the external bus clock. ECLK is used as a timing reference and for address demultiplexing. An active low bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state, and an output when COP or clock monitor causes a reset. Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin used in instruction tagging. See 16 Development Support. Indicates direction of data on expansion bus. Shares function with general-purpose I/O. Read/write in expanded modes. Maskable interrupt request input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). Provides a means of requesting asynchronous non-maskable interrupt requests after reset initialization. Single-wire background interface pin is dedicated to the background debug function. During reset, this pin determines special or normal operating mode. Pin used in instruction tagging. See 16 Development Support. BDLC receive pin BDLC transmit pin Slave select output for SPI master mode, input for slave mode or master mode. Serial clock for SPI system. Master out/slave in pin for serial peripheral interface Master in/slave out pin for serial peripheral interface SCI transmit pin SCI receive pin
RESET EXTAL XTAL LSTRB TAGLO R/W
32 33 34 35 35 36
IRQ
37
XIRQ BKGD TAGHI DLCRx DLCTx CS/SS SCK SDO/MOSI SDI/MISO TxD0 RxD0
38 17 17 76 75 68 67 66 65 62 61
MOTOROLA 14
MC68HC912B32 MC68HC912B32TS/D
3.4 Port Signals The MC68HC912B32 incorporates eight ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In addition to the pins described below, each port consists of a data register which can be read and written at any time, and, with the exception of port AD and PE[1:0], a data direction register which controls the direction of each pin. After reset all port pins are configured as input. 3.4.1 Port A Port A pins are used for address and data in expanded modes. The port data register is not in the address map during expanded and peripheral mode operation. When it is in the map, port A can be read or written at anytime. Register DDRA determines whether each port A pin is an input or output. DDRA is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRA makes the corresponding bit in port A an output; clearing a bit in DDRA makes the corresponding bit in port A an input. The default reset state of DDRA is all zeros. When the PUPA bit in the PUCR register is set, all port A input pins are pulled up internally by an active pull-up device. This bit has no effect if the port is being used in expanded modes as the pull-ups are inactive. Setting the RDPA bit in register RDRIV causes all port A outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to 6 Bus Control and Input/Output. 3.4.2 Port B Port B pins are used for address and data in expanded modes. The port data register is not in the address map during expanded and peripheral mode operation. When it is in the map, port B can be read or written at anytime. Register DDRB determines whether each port B pin is an input or output. DDRB is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRB makes the corresponding bit in port B an output; clearing a bit in DDRB makes the corresponding bit in port B an input. The default reset state of DDRB is all zeros. When the PUPB bit in the PUCR register is set, all port B input pins are pulled up internally by an active pull-up device. This bit has no effect if the port is being used in expanded modes as the pull-ups are inactive. Setting the RDPB bit in register RDRIV causes all port B outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to 6 Bus Control and Input/Output. 3.4.3 Port E Port E pins operate differently from port A and B pins. Port E pins are used for bus control signals and interrupt service request signals. When a pin is not used for one of these specific functions, it can be used as general-purpose I/O. However, two of the pins (PE[1:0]) can only be used for input, and the states of these pins can be read in the port data register even when they are used for IRQ and XIRQ. The PEAR register determines pin function, and register DDRE determines whether each pin is an input or output when it is used for general-purpose I/O. PEAR settings override DDRE settings. Because PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in the DDRE register makes the corresponding bit in port E an output; clearing a bit in the DDRE register makes the corresponding bit in port E an input. The default reset state of DDRE is all zeros.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 15
When the PUPE bit in the PUCR register is set, PE[7,3,2,0] are pulled up. PE[7,3,2,0] are pulled up active devices, while PE1 is always pulled up by means of an internal resistor. Neither port E nor DDRE is in the map in peripheral mode; neither is in the internal map in expanded modes with EME set. Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to 6 Bus Control and Input/Output. 3.4.4 Port DLC BDLC pins can be configured as general-purpose I/O port DLC. When BDLC functions are not enabled, the port has seven general-purpose I/O pins, PDLC[6:0]. The DLCSCR register controls port DLC function. The BDLC function, enabled with the BDLCEN bit, takes precedence over other port functions. Register DDRDLC determines whether each port DLC pin is an input or output. Setting a bit in DDRDLC makes the corresponding pin in port DLC an output; clearing a bit makes the corresponding pin an input. After reset port DLC pins are configured as inputs. When the PUPDLC bit in the DLCSCR register is set, all port DLC input pins are pulled up internally by an active pull-up device. Setting the RDPDLC bit in register DLCSCR causes all port DLC outputs to have reduced drive level. Levels are at normal drive capability after reset. RDPDLC can be written anytime after reset. Refer to 14 Byte Data Link Communications Module (BDLC). 3.4.5 Port AD Input to the analog-to-digital subsystem and general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD[7:0]. The ADPU bit in the ATDCTL2 register enables the A/D function. Port AD pins are inputs; no data direction register is associated with this port. The port has no resistive input loads and no reduced drive controls. Refer to 15 Analog-To-Digital Converter. 3.4.6 Port P The four pulse-width modulation channel outputs share general-purpose port P pins. The PWM function is enabled with the PWEN register. Enabling PWM pins takes precedence over the general-purpose port. When pulse-width modulation is not in use, the port pins may be used for general-purpose I/O. Register DDRP determines pin direction of port P when used for general-purpose I/O. When DDRP bits are set, the corresponding pin is configured for output. On reset the DDRP bits are cleared and the corresponding pin is configured for input. When the PUPP bit in the PWCTL register is set, all input pins are pulled up internally by an active pullup device. Pull-ups are disabled after reset. Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels. Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime after reset. Refer to 11 Pulse-Width Modulator. 3.4.7 Port T This port provides eight general-purpose I/O pins when not enabled for input capture and output compare in the timer and pulse accumulator subsystem. The TEN bit in the TSCR register enables the timer function. The pulse accumulator subsystem is enabled with the PAEN bit in the PACTL register.
MOTOROLA 16
MC68HC912B32 MC68HC912B32TS/D
Register DDRT determines pin direction of port T when used for general-purpose I/O. When DDRT bits are set, the corresponding pin is configured for output. On reset the DDRT bits are cleared and the corresponding pin is configured for input. When the PUPT bit in the TMSK2 register is set, all input pins are pulled up internally by an active pullup device. Pull-ups are disabled after reset. Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset. Refer to 12 Standard Timer Module. 3.4.8 Port S Port S is the 8-bit interface to the standard serial interface consisting of the serial communications interface (SCI) and serial peripheral interface (SPI) subsystems. Port S pins are available for general-purpose parallel I/O when standard serial functions are not enabled. Port S pins serve several functions depending on the various internal control registers. If WOMS bit in the SC0CR1 register is set, the P-channel drivers of the output buffers are disabled for bits 0 through 1 (2 through 3). If SWOM bit in the SP0CR1 register is set, the P-channel drivers of the output buffers are disabled for bits 4 through 7. (wired-OR mode). The open drain control effects both the serial and the general-purpose outputs. If the RDPSx bits in the PURDS register are set, the appropriate port S pin drive capabilities are reduced. If PUPSx bits in the PURDS register are set, the appropriate pull-up device is connected to each port S pin which is programmed as a general-purpose input . If the pin is programmed as a general-purpose output, the pull-up is disconnected from the pin regardless of the state of the individual PUPSx bits. See 13 Serial Interface.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 17
Table 6 MC68HC912B32 Port Description Summary
Port Name Port A PA[7:0] Pin Numbers 46-39 Data Direction DD Register (Address) In/Out DDRA ($0002) In/Out DDRB ($0003) Description Port A and port B pins are used for address and data in expanded modes. The port data registers are not in the address map during expanded and peripheral mode operation. When in the map, port A and port B can be read or written any time. DDRA and DDRB are not in the address map in expanded or peripheral modes. 58-51 70-76 In In/Out DDRDLC ($00FF) PE[1:0] In PE[7:2] In/Out DDRE ($0009) In/Out DDRP ($0057) In/Out DDRS ($00D7) In/Out DDRT ($00AF) Analog-to-digital converter and general-purpose I/O. Byte Data Link Communication (BDLC) subsystem and general-purpose I/O. Mode selection, bus control signals and interrupt service request signals; or general-purpose I/O. General-purpose I/O. PP[3:0] are use with the pulse-width modulator when enabled. Serial communications interface and serial peripheral interface subsystems and general-purpose I/O. General-purpose I/O when not enabled for input capture and output compare in the timer and pulse accumulator subsystem.
Port B PB[7:0]
25-18
Port AD PAD[7:0] Port DLC PDLC[6:0] Port E PE[7:0] Port P PP[7:0] Port S PS[7:0] Port T PT[7:0]
26-29, 35-38
79, 80, 1-6 68-61
16-12, 9-7
MOTOROLA 18
MC68HC912B32 MC68HC912B32TS/D
3.5 Port Pull-Up, Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. Table 7 summarizes the port pull-up default status and controls. Table 7 Port Pull-Up, Pull-Down and Reduced Drive Summary
Enable Bit Port Name Port A Port B Port E: PE7, PE3, PE2, PE0 PE1 PE[6:4] PE[6:5] Port P Port S PS[3:2] PS[7:4] Port T Port DLC Port AD BKGD Pull-up Pull-up None Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up None Pull-up -- PWCTL ($0054) PURDS ($00DB) PURDS ($00DB) PURDS ($00DB) TMSK2 ($008D) PUCR ($000C) PUPE Enabled RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) -- Disabled Disabled Disabled Disabled Disabled Disabled Enabled PWCTL ($0054) PURDS ($00DB) PURDS ($00DB) PURDS ($00DB) TMSK2 ($008D) RDPE RDPE RDPE -- RDPP RDPS0 RDPS1 RDPS2 RDPT -- -- -- -- Full Drive Full Drive Full Drive Full Drive -- Full Drive Full Drive Full Drive Full Drive Full Drive Full Drive Resistive Input Loads Pull-up Pull-up Register (Address) PUCR ($000C) PUCR ($000C) Bit Name Reset State PUPA PUPB Disabled Disabled Reduced Drive Control Bit Register (Address) RDRIV ($000D) RDRIV ($000D) Bit Name RDPA RDPB Reset State Full Drive Full Drive
Always Enabled -- Enabled During Reset PUPP PUPS0 PUPS1 PUPS2 PUPT --
DLCSCR ($00FD) DLCPUE
DLCSCR ($00FD) DLCRDV
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 19
4 Register Block
The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block's 16-bit address. The register block occupies the first 512 bytes of the 2-Kbyte block. Default addressing (after reset) is indicated in the table below. For additional information refer to 5 Operating Modes and Resource Mapping. Table 8 MC68HC912B32 Register Map (Sheet 1 of 5)
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C- $001D $001E $001F $0020 $0021 $0022 Bit 7 PA7 PB7 DDA7 DDB7 0 0 0 0 PE7 DDE7 NDBE SMODN 0 0 0 0 RAM15 REG15 EE15 0 RTIE RTIF CME Bit 7 ITE6 ITD6 ITC6 0 0 IRQE 1 BKEN1 0 Bit 15 6 PA6 PB6 DDA6 DDB6 0 0 0 0 PE6 DDE6 0 MODB 0 0 0 0 RAM14 REG14 EE14 NDRF RSWAI 0 FCME 6 ITE8 ITD8 ITC8 0 0 IRQEN 1 BKEN0 BKDBE 14 5 PA5 PB5 DDA5 DDB5 0 0 0 0 PE5 DDE5 PIPOE MODA 0 0 0 0 RAM13 REG13 EE13 RFSTR1 RSBCK 0 FCM 5 ITEA ITDA ITCA 0 0 DLY PSEL5 BKPM BKMBH 13 4 PA4 PB4 DDA4 DDB4 0 0 0 0 PE4 DDE4 NECLK ESTR PUPE 0 0 0 RAM12 REG12 EE12 RFSTR0 0 0 FCOP 4 ITEC ITDC ITCC 0 0 0 PSEL4 0 BKMBL 12 3 PA3 PB3 DDA3 DDB3 0 0 0 0 PE3 DDE3 LSTRE IVIS 0 RDPE 0 0 RAM11 REG11 0 EXSTR1 RTBYP 0 DISR 3 ITEE ITDE ITCE 0 0 0 PSEL3 BK1ALE BK1RWE 11 2 PA2 PB2 DDA2 DDB2 0 0 0 0 PE2 DDE2 RDWE EBSWAI 0 0 0 0 0 0 0 EXSTR0 RTR2 0 CR2 2 ITF0 ITE0 ITD0 ITC0 0 0 PSEL2 BK0ALE BK1RW 10 1 PA1 PB1 DDA1 DDB1 0 0 0 0 PE1 0 0 0 PUPB RDPB 0 0 0 0 0 MAPROM RTR1 0 CR1 1 ITF2 ITE2 ITD2 ITC2 0 0 PSEL1 0 BK0RWE 9 Bit 0 PA0 PB0 DDA0 DDB0 0 0 0 0 PE0 0 0 EME PUPA RDPA 0 0 0 MMSWAI EEON ROMON RTR0 0 CR0 Bit 0 ITF4 ITE4 ITD4 ITC4 0 0 0 0 BK0RW Bit 8 Name PORTA1 PORTB1 DDRA1 DDRB1 Reserved Reserved Reserved Reserved PORTE2 DDRE2 PEAR2 MODE3 PUCR3 RDRIV3 Reserved Reserved INITRM INITRG INITEE MISC RTICTL RTIFLG COPCTL COPRST ITST0 ITST1 ITST2 ITST3 Reserved INTCR HPRIO BRKCT0 BRKCT1 BRKAH
MOTOROLA 20
MC68HC912B32 MC68HC912B32TS/D
Table 8 MC68HC912B32 Register Map (Sheet 2 of 5)
Address $0023 $0024 $0025 $0026- $003F $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058- $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A- $006E Bit 7 Bit 7 Bit 15 Bit 7 0 CON23 PCLK3 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 0 DISCR PP7 DDP7 0 0 0 ADPU 0 0 0 SCF CCF7 SAR9 SAR1 0 6 6 14 6 0 CON01 PCLK2 0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 0 DISCP PP6 DDP6 0 0 0 AFFC 0 SMP1 S8CM 0 CCF6 SAR8 SAR0 0 5 5 13 5 0 PCKA2 PCLK1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 0 DISCAL PP5 DDP5 0 0 0 ASWAI 0 SMP0 SCAN 0 CCF5 SAR7 RST 0 4 4 12 4 0 PCKA1 PCLK0 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PSWAI 0 PP4 DDP4 0 0 0 0 0 PRS4 MULT 0 CCF4 SAR6 TSTOUT 0 3 3 11 3 0 PCKA0 PPOL3 PWEN3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CENTR 0 PP3 DDP3 0 0 0 0 0 PRS3 CD 0 CCF3 SAR5 TST3 0 2 2 10 2 0 PCKB2 PPOL2 PWEN2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDPP 0 PP2 DDP2 0 0 0 0 0 PRS2 CC CC2 CCF2 SAR4 TST2 0 1 1 9 1 0 PCKB1 PPOL1 PWEN1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PUPP 0 PP1 DDP1 0 0 0 ASCIE FRZ1 PRS1 CB CC1 CCF1 SAR3 TST1 0 Bit 0 Bit 0 Bit 8 Bit 0 0 PCKB0 PPOL0 PWEN0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PSBCK 0 PP0 DDP0 0 0 0 ASCIF FRZ0 PRS0 CA CC0 CCF0 SAR2 TST0 0 Name BRKAL BRKDH BRKDL Reserved PWCLK PWPOL PWEN PWPRES PWSCAL0 PWSCNT0 PWSCAL1 PWSCNT1 PWCNT0 PWCNT1 PWCNT2 PWCNT3 PWPER0 PWPER1 PWPER2 PWPER3 PWDTY0 PWDTY1 PWDTY2 PWDTY3 PWCTL PWTST PORTP DDRP Reserved ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT ATDSTAT ATDTSTH ATDTSTL Reserved
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 21
Table 8 MC68HC912B32 Register Map (Sheet 3 of 5)
Address $006F $0070 $0071 $0072 $0073 $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B $007C $007D $007E $007F $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 Bit 7 PAD7 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 IOS7 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN 0 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 6 PAD6 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 IOS6 FOC6 OC7M6 OC7D6 14 6 TSWAI 0 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 14 5 PAD5 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 IOS5 FOC5 OC7M5 OC7D5 13 5 TSBCK 0 OM6 OM2 EDG6B EDG2B C5I PUPT C5F 0 13 5 13 5 13 5 13 5 13 4 PAD4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IOS4 FOC4 OC7M4 OC7D4 12 4 TFFCA 0 OL6 OL2 EDG6A EDG2A C4I RDPT C4F 0 12 4 12 4 12 4 12 4 12 3 PAD3 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 IOS3 FOC3 OC7M3 OC7D3 11 3 0 0 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 11 3 11 3 11 3 11 3 11 2 PAD2 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 IOS2 FOC2 OC7M2 OC7D2 10 2 0 0 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 10 1 PAD1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 IOS1 FOC1 OC7M1 OC7D1 9 1 0 0 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 9 Bit 0 PAD0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 IOS0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Name PORTAD ADR0H Reserved ADR1H Reserved ADR2H Reserved ADR3H Reserved ADR4H Reserved ADR5H Reserved ADR6H Reserved ADR7H Reserved TIOS CFORC OC7M OC7D TCNT (H) TCNT (L) TSCR TQCR TCTL1 TCTL2 TCTL3 TCTL4 TMSK1 TMSK2 TFLG1 TFLG2 TC0 (H) TC0 (L) TC1 (H) TC1 (L) TC2 (H) TC2 (L) TC3 (H) TC3 (L) TC4 (H)
MOTOROLA 22
MC68HC912B32 MC68HC912B32TS/D
Table 8 MC68HC912B32 Register Map (Sheet 4 of 5)
Address $0099 $009A $009B $009C $009D $009E $009F $00A0 $00A1 $00A2 $00A3 $00A4- $00AC $00AD $00AE $00AF $00B0- $00BF $00C0 $00C1 $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 $00C8- $00CF $00D0 $00D1 $00D2 $00D3 $00D4 $00D5 $00D6 $00D7 $00D8- $00DA $00DB $00DC- $00EF $00F0 $00F1 Bit 7 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 0 0 Bit 15 Bit 7 0 0 PT7 DDT7 0 BTST SBR7 LOOPS TIE TDRE 0 R8 R7/T7 0 SPIE 0 0 SPIF 0 Bit 7 PS7 DDS7 0 0 0 1 1 6 6 14 6 14 6 14 6 PAEN 0 14 6 0 0 PT6 DDT6 0 BSPL SBR6 WOMS TCIE TC 0 T8 R6/T6 0 SPE 0 0 WCOL 0 6 PS6 DDS6 0 RDPS2 0 1 1 5 5 13 5 13 5 13 5 PAMOD 0 13 5 0 0 PT5 DDT5 0 BRLD SBR5 RSRC RIE RDRF 0 0 R5/T5 0 SWOM 0 0 0 0 5 PS5 DDS5 0 RDPS1 0 1 1 4 4 12 4 12 4 12 4 PEDGE 0 12 4 0 0 PT4 DDT4 0 SBR12 SBR4 M ILIE IDLE 0 0 R4/T4 0 MSTR 0 0 MODF 0 4 PS4 DDS4 0 RDPS0 0 1 BPROT4 3 3 11 3 11 3 11 3 CLK1 0 11 3 0 0 PT3 DDT3 0 SBR11 SBR3 WAKE TE OR 0 0 R3/T3 0 CPOL 0 0 0 0 3 PS3 DDS3 0 0 0 1 BPROT3 2 2 10 2 10 2 10 2 CLK0 0 10 2 0 0 PT2 DDT2 0 SBR10 SBR2 ILT RE NF 0 0 R2/T2 0 CPHA 0 SPR2 0 0 2 PS2 DDS2 0 PUPS2 0 EESWAI BPROT2 1 1 9 1 9 1 9 1 PAOVI PAOVF 9 1 0 TCBYP PT1 DDT1 0 SBR9 SBR1 PE RWU FE 0 0 R1/T1 0 SSOE SSWAI SPR1 0 0 1 PS1 DDS1 0 PUPS1 0 PROTLCK BPROT1 Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 8 Bit 0 0 PCBYP PT0 DDT0 0 SBR8 SBR0 PT SBK PF RAF 0 R0/T0 0 LSBF SPC0 SPR0 0 0 Bit 0 PS0 DDS0 0 PUPS0 0 EERC BPROT0 Name TC4 (L) TC5 (H) TC5 (L) TC6 (H) TC6 (L) TC7 (H) TC7 (L) PACTL PAFLG PACNT PACNT Reserved TIMTST PORTT DDRT Reserved SC0BDH SC0BDL SC0CR1 SC0CR2 SC0SR1 SC0SR2 SC0DRH SC0DRL Reserved SP0CR1 SP0CR2 SP0BR SP0SR Reserved SP0DR PORTS DDRS Reserved PURDS Reserved EEMCR EEPROT
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 23
Table 8 MC68HC912B32 Register Map (Sheet 5 of 5)
Address $00F2 $00F3 $00F4 $00F5 $00F6 $00F7 $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF $0100- $01FF Bit 7 EEODD BULKP 0 0 FSTE 0 IMSG 0 ALOOP D7 ATE 0 0 0 0 6 EEVEN 0 0 0 GADR 0 CLKS 0 DLOOP D6 RXPOL 0 PDLC6 DDDLC6 0 5 MARG 0 0 0 HVT 0 R1 I3 RX4XE D5 0 0 PDLC5 DDDLC5 0 4 EECPD BYTE 0 0 FENLV FEESWAI R0 I2 NBFS D4 0 0 PDLC4 DDDLC4 0 3 EECPRD ROW 0 0 FDISVFP SVFP 0 I1 TEOD D3 BO3 0 PDLC3 DDDLC3 0 2 0 ERASE 0 0 VTCK ERAS 0 I0 TSIFR D2 BO2 BDLCEN PDLC2 DDDLC2 0 1 EECPM EELAT 0 0 STRE LAT IE 0 TMIFR1 D1 BO1 DLCPUE PDLC1 DDDLC1 0 Bit 0 0 EEPGM LOCK BOOTP MWPR ENPE WCM 0 TMIFR0 D0 BO0 DLCRDV PDLC0 DDDLC0 0 Name EETST EEPROG FEELCK FEEMCR FEETST FEECTL BCR1 BSVR BCR2 BDR BARD DLCSCR PORTDLC DDRDLC Reserved
NOTES: 1. Port A, port B, and data direction registers DDRA and DDRB are not in map in expanded and peripheral modes. 2. Port E and DDRE not in map in peripheral mode; also not in map in expanded modes with EME set. 3. Not in map in peripheral mode.
MOTOROLA 24
MC68HC912B32 MC68HC912B32TS/D
5 Operating Modes and Resource Mapping
Eight possible operating modes determine the operating configuration of the MC68HC912B32. Each mode has an associated default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 5.1 Operating Modes The operating mode out of reset is determined by the states of the BKGD, MODB, and MODA pins during reset. The SMODN, MODB, and MODA bits in the MODE register show current operating mode and provide limited mode switching during operation. The states of the BKGD, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. During reset an active pull-up is connected to the BKGD pin (as input) and active pulldowns are connected to the MODB and MODA pins. If an open occurs on any of these pins, the device will operate in normal single-chip mode. Table 9 Mode Selection
BKGD MODB MODA 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Mode Special Single Chip Special Expanded Narrow Special Peripheral Special Expanded Wide Normal Single Chip Normal Expanded Narrow Reserved (Forced to Peripheral) Normal Expanded Wide Port A General-Purpose I/O ADDR[15:8]/DATA[15:0] ADDR/DATA ADDR/DATA General-Purpose I/O ADDR[15:8]/DATA[15:0] -- ADDR/DATA Port B General-Purpose I/O ADDR[7:0] ADDR/DATA ADDR/DATA General-Purpose I/O ADDR[7:0] -- ADDR/DATA
There are two basic types of operating modes: Normal modes -- some registers and bits are protected against accidental changes. Special modes -- allow greater access to protected control registers and bits for special purposes such as testing and emulation. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. 5.1.1 Normal Operating Modes These modes provide three operating configurations. Background debugging is available in all three modes, but must first be enabled for some operations by means of a BDM command. BDM can then be made active by another BDM command. Normal Expanded Wide Mode -- This is a normal mode of operation in which the address and data are multiplexed onto ports A and B. ADDR[15:8] and DATA[15:8] are present on port A. ADDR[7:0] and DATA[7:0] are present on port B. Normal Expanded Narrow Mode -- Port A is configured as the high byte of address multiplexed with the 8-bit data bus. Port B is configured as the lower 8-bit address bus. This mode is used for lower cost production systems that use 8-bit wide external EEPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 25
Normal Single-Chip Mode -- There are no external address and data buses in this mode. All pins of ports A, B and E are configured as general-purpose I/O pins. Port E bits 1 and 0 are input-only with internal pull-ups and the other 22 pins are bidirectional I/O pins that are initially configured as high-impedance inputs. Port E pull-ups are enabled upon reset; port A and B pull-ups are disabled upon reset. 5.1.2 Special Operating Modes There are three special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. In addition, there is a special peripheral mode, in which an external master, such as an I.C. tester, can control the on-chip peripherals. Special Expanded Wide Mode -- This mode can be used for emulation of normal expanded wide mode and emulation of normal single-chip mode and 16-bit data bus. The bus control related pins in PORTE are all configured to serve their bus control output functions rather than general-purpose I/O. Special Expanded Narrow Mode -- This mode can be used for emulation of normal expanded narrow mode. In this mode external 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. Internal operations continue to use full 16-bit data paths. Special Single-Chip Mode -- This mode can be used to force the MCU to active BDM mode to allow system debug through the BKGD pin. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead, the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There are no external address and data buses in this mode. The MCU operates as a stand-alone device and all program and data space are on-chip. External port pins can be used for general-purpose I/O. Special Peripheral Mode -- The CPU is not active in this mode. An external master can control onchip peripherals for testing purposes. It is not possible to change to or from this mode without going through reset. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both modes. 5.2 Background Debug Mode Background debug mode (BDM) is an auxiliary operating mode that is used for system development. BDM is implemented in on-chip hardware and provides a full set of debug operations. Some BDM commands can be executed while the CPU is operating normally. Other BDM commands are firmware based, and require the BDM firmware to be enabled and active for execution. In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in all other operating modes, but must be enabled before it can be activated. BDM should not be used in special peripheral mode because of potential bus conflicts. Once enabled, background mode can be made active by a serial command sent via the BKGD pin or execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret special debugging commands, and read and write CPU registers, peripheral registers, and locations in memory. While BDM is active, the CPU executes code located in a small on-chip ROM mapped to addresses $FF00 to $FFFF; BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM replaces the regular system vectors while BDM is active. While BDM is active, the user memory from $FF00 to $FFFF is not in the map except through serial BDM commands. BDM allows read and write access to internal memory-mapped registers and RAM, and read access to EEPROM and Flash EEPROM without interrupting the application code executing in the CPU. This nonintrusive mode uses dead bus cycles to access the memory and in most cases will remain cycle deterministic. Refer to 16 Development Support for more details on BDM.
MOTOROLA 26
MC68HC912B32 MC68HC912B32TS/D
MODE -- Mode Register
Bit 7 SMODN RESET: RESET: RESET: RESET: RESET: RESET: RESET: 1 1 0 0 0 1 0 6 MODB 0 1 0 1 1 0 0 5 MODA 1 1 1 1 0 0 0 4 ESTR 1 1 1 1 1 1 1 3 IVIS 0 0 1 1 1 0 1 2 EBSWAI 0 0 0 0 0 0 0 1 0 - - - - - - - Bit 0 EME 0 0 1 1 1 0 1
$000B
Normal Exp Narrow Normal Exp Wide Special Exp Narrow Special Exp Wide Peripheral Normal Single Chip Special Single Chip
MODE controls the MCU operating mode and various configuration options. This register is not in the map in peripheral mode. SMODN, MODB, MODB -- Mode Select Special, B and A These bits show the current operating mode and reflect the status of the BKGD, MODB and MODA input pins at the rising edge of reset. Read anytime. SMODN may only be written if SMODN = 0 (in special modes) but the first write is ignored; MODB, MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special peripheral and reserved modes cannot be selected. ESTR -- E Clock Stretch Enable Determines if the E Clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. ESTR is always one in expanded modes since it is required for address demultiplexing and must follow stretched cycles. 0 = E never stretches (always free running). 1 = E stretches high during external access cycles and low during non-visible internal accesses. Normal modes: write once; Special modes: write anytime, read anytime. IVIS -- Internal Visibility This bit determines whether internal ADDR/DATA, R/W, and LSTRB signals can be seen on the bus during accesses to internal locations. In special expanded narrow mode, it is possible to configure the MCU to show internal accesses on an external 16-bit bus. The IVIS control bit must be set to one. When the system is configured this way, visible internal accesses are shown as if the MCU was configured for expanded wide mode but normal external accesses operate as if the bus was in narrow mode. In normal expanded narrow mode, internal visibility is not allowed and IVIS is ignored. 0 = No visibility of internal bus operations on external bus 1 = Internal bus operations are visible on external bus Normal modes: write once; Special modes: write anytime EXCEPT the first time. Read anytime. EBSWAI -- External Bus Module Stop in Wait Control This bit controls access to the external bus interface when in wait mode. The module will delay before shutting down in wait mode to allow for final bus activity to complete. 0 = External bus and registers continue functioning during wait mode. 1 = External bus is shut down during wait mode.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 27
EME -- Emulate Port E Removing the registers from the map allows the user to emulate the function of these registers externally. In single-chip mode PORTE and DDRE are always in the map regardless of the state of this bit. 0 = PORTE and DDRE are in the memory map. 1 = PORTE and DDRE are removed from the internal memory map (expanded mode). Normal modes: write once; special modes: write anytime EXCEPT the first time. Read anytime. 5.3 Internal Resource Mapping The internal register block, RAM, Flash EEPROM and EEPROM have default locations within the 64Kbyte standard address space but may be reassigned to other locations during program execution by setting bits in mapping registers INITRG, INITRM, and INITEE. During normal operating modes these registers can be written once. It is advisable to explicitly establish these resource locations during the initialization phase of program execution, even if default values are chosen, in order to protect the registers from inadvertent modification later. Writes to the mapping registers go into effect between the cycle that follows the write and the cycle after that. To assure that there are no unintended operations, a write to one of these registers should be followed with a NOP instruction. If conflicts occur when mapping resources, the register block will take precedence over the other resources; RAM, Flash EEPROM, or EEPROM addresses occupied by the register block will not be available for storage. When active, BDM ROM takes precedence over other resources although a conflict between BDM ROM and register space is not possible. Table 10 shows resource mapping precedence. All address space not utilized by internal resources is by default external memory. The memory expansion module manages three memory overlay windows: program, data, and one extra page overlay. The size and location of the program and data overlay windows are fixed. One of two locations can be selected for the extra page (EPAGE). Table 10 Mapping Precedence
Precedence 1 2 3 4 5 6 Resource BDM ROM (if active) Register Space RAM EEPROM Flash EEPROM External Memory
5.3.1 Register Block Mapping After reset the 512 byte register block resides at location $0000 but can be reassigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal registers is controlled by five bits in the INITRG register. The register block occupies the first 512 bytes of the 2-Kbyte block. INITRG -- Initialization of Internal Register Position Register
Bit 7 REG15 RESET: 0 6 REG14 0 5 REG13 0 4 REG12 0 3 REG11 0 2 0 0 1 0 0 Bit 0 MMSWAI 0
$0011
REG[15:11] -- Internal register map position These bits specify the upper five bits of the 16-bit registers address. Write once in normal modes or anytime in special modes. Read anytime.
MOTOROLA 28
MC68HC912B32 MC68HC912B32TS/D
MMSWAI -- Memory Mapping Interface Stop in Wait Control This bit controls access to the memory mapping interface when in Wait mode. 0 = Memory mapping interface continues to function during Wait mode. 1 = Memory mapping interface access is shut down during Wait mode. 5.3.2 RAM Mapping The MC68HC912B32 has 1 Kbyte of fully static RAM that is used for storing instructions, variables, and temporary data during program execution. After reset, RAM addressing begins at location $0800 but can be assigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal RAM is controlled by five bits in the INITRM register. The RAM array occupies the first 1 Kbyte of the 2-Kbyte block. INITRM -- Initialization of Internal RAM Position Register
Bit 7 RAM15 RESET: 0 6 RAM14 0 5 RAM13 0 4 RAM12 0 3 RAM11 1 2 0 0 1 0 0 Bit 0 0 0
$0010
RAM[15:11] -- Internal RAM Map Position These bits specify the upper five bits of the 16-bit RAM address. Write once in normal modes or anytime in special modes. Read anytime. 5.3.3 EEPROM Mapping The MC68HC912B32 has 768 bytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset EEPROM address space begins at location $0D00 but can be mapped to any 4-Kbyte boundary within the standard 64-Kbyte address space. INITEE -- Initialization of Internal EEPROM Position Register
Bit 7 EE15 RESET: 0 6 EE14 0 5 EE13 0 4 EE12 0 3 0 0 2 0 0 1 0 0 Bit 0 EEON 1
$0012
EE[15:12] -- Internal EEPROM map position These bits specify the upper four bits of the 16-bit EEPROM address. Write once in normal modes or anytime in special modes. Read anytime. EEON -- Internal EEPROM On (Enabled) The EEON bit allows read access to the EEPROM array. EEPROM control registers can be accessed and EEPROM locations may be programmed or erased regardless of the state of EEON. This bit is forced to one in single-chip modes. Read or write anytime. 0 = Removes the EEPROM from the map 1 = Places the on-chip EEPROM in the memory map 5.3.4 Flash EEPROM and Expansion Address Mapping Additional mapping controls are available that can be used in conjunction with Flash EEPROM and memory expansion.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 29
The 32-Kbyte Flash EEPROM can be mapped to either the upper or lower half of the 64-Kbyte address space. When mapping conflicts occur, registers, RAM and EEPROM have priority over Flash EEPROM. To use memory expansion the part must be operated in one of the expanded modes. MISC -- Miscellaneous Mapping Control Register
Bit 7 0 RESET: 0 6 NDRF 0 5 RFSTR1 0 4 RFSTR0 0 3 EXSTR1 0 2 EXSTR0 0 1 MAPROM 0 Bit 0 ROMON 0
$0013
This register can be read anytime. In normal modes MISC can be written once; in special modes it can be written anytime. NDRF -- Narrow Data Bus for Register-Following Map This bit enables a narrow bus feature for the 512-byte register-following map. In expanded narrow (eight bit) modes, single-chip modes, and peripheral mode, NDRF has no effect. The register-following map always begins at the byte following the 512-byte register map. If the registers are moved this space will also move. 0 = Register-following map space acts as a full 16-bit data bus 1 = Register-following map space acts the same as an 8-bit external data bus RFSTR1, RFSTR0 -- Register-Following Stretch Bit 1 and Bit 0 These bits determine the amount of clock stretch on accesses to the 512-byte register-following map. It is valid regardless of the state of the NDRF bit. In single-chip and peripheral modes this bit has no meaning or effect. Table 11 Register-Following Stretch-Bit Definition
Stretch Bit RFSTR1 Stretch Bit RFSTR0 E Clocks Stretched 0 0 1 1 0 1 0 1 0 1 2 3
EXSTR1, EXSTR0 -- External Access Stretch Bit 1 and Bit 0 These bits determine the amount of clock stretch on accesses to the external address space. In singlechip and peripheral modes this bit has no meaning or effect. Table 12 Expanded Stretch-Bit Definition
Stretch Bit EXSTR1 Stretch Bit EXSTR0 E Clocks Stretched 0 0 1 1 0 1 0 1 0 1 2 3
MAPROM -- Map Location of Flash EEPROM This bit determines the location of the on-chip Flash EEPROM. In expanded modes it is reset to zero. In single-chip modes it is reset to one. If ROMON is zero, this bit has no meaning or effect. 0 = Flash EEPROM is located from $0000 to $7FFF 1 = Flash EEPROM is located from $8000 to $FFFF
MOTOROLA 30
MC68HC912B32 MC68HC912B32TS/D
ROMON -- Enable Flash EEPROM In expanded modes ROMON is reset to zero. In single-chip modes it is reset to one. If the internal RAM, registers, EEPROM, or BDM ROM (if active) are mapped to the same space as the Flash EEPROM, they will have priority over the Flash EEPROM. 0 = Disables the Flash EEPROM in the memory map 1 = Enables the Flash EEPROM in the memory map 5.4 Memory Maps The following diagrams illustrate the memory map for each mode of operation immediately after reset.
$0000
$0000 REGISTERS 512 BYTES RAM $01FF MAP TO ANY 2K SPACE $0200 REGISTER FOLLOWING SPACE $03FF 512 BYTES RAM $0800 $0BFF 1-KBYTE RAM MAP TO ANY 2K SPACE 768 BYTES EEPROM MAP TO ANY 4K SPACE $0FFF
$0000
$0800
$0D00
$0D00
$8000
$7FFF $8000
FLASH EEPROM MAP WITH MAPROM BIT IN MISC REGISTER TO $0000 - $7FFF OR $8000 - $FFFF $FF00 $F000 $FF00 $FFC0 $FFFF
BDM (IF ACTIVE) $FFFF
VECTORS
VECTORS
VECTORS
$FFFF
EXPANDED
SINGLE CHIP NORMAL
SINGLE CHIP SPECIAL
HC812B32 MEM MAP
Figure 6 MC68HC912B32 Memory Map
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 31
6 Bus Control and Input/Output
Internally the MC68HC912B32 has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or sixteen bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8- or 16-bit data. 6.1 Detecting Access Type from External Signals The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that produce LSTRB=A0=1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus (data order is swapped). Table 13 Access Type vs. Bus Control Pins
LSTRB 1 0 1 0 0 1 0 1 A0 0 1 0 1 0 1 0 1 R/W 1 1 0 0 1 1 0 0 Type of Access 8-bit read of an even address 8-bit read of an odd address 8-bit write to an even address 8-bit write to an odd address 16-bit read of an even address 16-bit read of an odd address (low/high data swapped) 16-bit write to an even address 16-bit write to an even address (low/high data swapped)
6.2 Registers Not all registers are visible in the MC68HC912B32 memory map under certain conditions. In special peripheral mode the first 16 registers associated with bus expansion are removed from the memory map. In expanded modes, some or all of port A, port B, and port E are used for expansion buses and control signals. In order to allow emulation of the single-chip functions of these ports, some of these registers must be rebuilt in an external port replacement unit. In any expanded mode port A and port B are used for address and data lines so registers for these ports, as well as the data direction registers for these ports, are removed from the on-chip memory map and become external accesses. In any expanded mode, port E pins may be needed for bus control (e.g., ECLK, R/W). To regain the single-chip functions of port E, the emulate port E (EME) control bit in the MODE register may be set. In this special case of expanded mode and EME set, PORTE and DDRE registers are removed from the on-chip memory map and become external accesses so port E may be rebuilt externally.
MOTOROLA 32
MC68HC912B32 MC68HC912B32TS/D
PORTA -- Port A Register
Bit 7 Single Chip RESET: Exp Wide & Periph: PA7 - ADDR15 DATA15 6 PA6 - ADDR14 DATA14 5 PA5 - ADDR13 DATA13 4 PA4 - ADDR12 DATA12 3 PA3 - ADDR11 DATA11 2 PA2 - ADDR10 DATA10 1 PA1 - ADDR9 DATA9 Bit 0 PA0 - ADDR8 DATA8 ADDR8 DATA8/0
$0000
Expanded ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 Narrow DATA15/7 DATA14/6 DATA13/5 DATA12/4 DATA11/3 DATA10/2 DATA9/1
Bits PA[7:0] are associated with addresses ADDR[15:8] and DATA[15:8]. When this port is not used for external addresses and data, such as in single-chip mode, these pins can be used as general-purpose I/O. DDRA determines the primary direction of each pin. This register is not in the on-chip map in expanded and peripheral modes. Read and write anytime. DDRA -- Port A Data Direction Register
Bit 7 DDA7 RESET: 0 6 DDA6 0 5 DDA5 0 4 DDA4 0 3 DDA3 0 2 DDA2 0 1 DDA1 0 Bit 0 DDA0 0
$0002
This register determines the primary direction for each port A pin when functioning as a general-purpose I/O port. DDRA is not in the on-chip map in expanded and peripheral modes. Read and write anytime. 0 = Associated pin is a high-impedance input 1 = Associated pin is an output PORTB -- Port B Register
Bit 7 Single Chip RESET: Exp Wide & Periph: Expanded Narrow PB7 - ADDR7 DATA7 ADDR7 6 PB6 - ADDR6 DATA6 ADDR6 5 PB5 - ADDR5 DATA5 ADDR5 4 PB4 - ADDR4 DATA4 ADDR4 3 PB3 - ADDR3 DATA3 ADDR3 2 PB2 - ADDR2 DATA2 ADDR2 1 PB1 - ADDR1 DATA1 ADDR1 Bit 0 PB0 - ADDR0 DATA0 ADDR0
$0001
Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]. When this port is not used for external addresses and data such as in single-chip mode, these pins can be used as general-purpose I/O. DDRB determines the primary direction of each pin. This register is not in the on-chip map in expanded and peripheral modes. Read and write anytime. DDRB -- Port B Data Direction Register
Bit 7 DDB7 RESET: 0 6 DDB6 0 5 DDB5 0 4 DDB4 0 3 DDB3 0 2 DDB2 0 1 DDB1 0 Bit 0 DDB0 0
$0003
This register determines the primary direction for each port B pin when functioning as a general-purpose I/O port. DDRB is not in the on-chip map in expanded and peripheral modes. Read and write anytime. 0 = Associated pin is a high-impedance input 1 = Associated pin is an output
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 33
PORTE -- Port E Register
Bit 7 Single Chip RESET: Alt. Pin Function PE7 - DBE 6 PE6 - MODB or IPIPE1 5 PE5 - MODA or IPIPE0 4 PE4 - ECLK 3 PE3 - LSTRB or TAGLO 2 PE2 - R/W 1 PE1 - IRQ Bit 0 PE0 - XIRQ
$0008
This register is associated with external bus control signals and interrupt inputs including data bus enable (DBE), mode select (MODB/IPIPE1, MODA/IPIPE0), E clock, data size (LSTRB/TAGLO), read/ write (R/W), IRQ, and XIRQ. When the associated pin is not used for one of these specific functions, the pin can be used as general-purpose I/O. The port E assignment register (PEAR) selects the function of each pin. DDRE determines the primary direction of each port E pin when configured to be generalpurpose I/O. Some of these pins have software selectable pull-ups (DBE, LSTRB, R/W, and XIRQ). A single control bit enables the pull-ups for all these pins which are configured as inputs. IRQ always has a pull-up. This register is not in the map in peripheral mode or expanded modes when the EME bit is set. Read and write anytime. DDRE -- Port E Data Direction Register
Bit 7 DDE7 RESET: 0 6 DDE6 0 5 DDE5 0 4 DDE4 0 3 DDE3 0 2 DDE2 0 1 0 - Bit 0 0 -
$0009
This register determines the primary direction for each port E pin configured as general-purpose I/O. 0 = Associated pin is a high-impedance input 1 = Associated pin is an output PE[1:0] are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be read regardless of whether the alternate interrupt functions are enabled. This register is not in the map in peripheral mode and expanded modes while the EME control bit is set. Read and write anytime. PEAR -- Port E Assignment Register
Bit 7 NDBE RESET: RESET: RESET: RESET: RESET: 0 0 1 1 0 6 0 - - - - - 5 PIPOE 0 1 0 0 1 4 NECLK 0 0 1 1 0 3 LSTRE 0 1 0 0 1 2 RDWE 0 1 0 0 1 1 0 - - - - - Bit 0 0 - - - - - Normal Expanded Special Expanded Peripheral Normal Single Chip Special Single Chip
$000A
The PEAR register is used to choose between the general-purpose I/O functions and the alternate bus control functions of port E. When an alternate control function is selected, the associated DDRE bits are overridden. The reset condition of this register depends on the mode of operation because bus-control signals are needed immediately after reset in some modes. In normal single-chip mode, no external bus control signals are needed so all of port E is configured for general-purpose I/O.
MOTOROLA 34
MC68HC912B32 MC68HC912B32TS/D
In special single-chip mode, the E clock is enabled as a timing reference and the other bits of port E are configured for general-purpose I/O. In normal expanded modes, the reset vector is located in external memory. The E clock may be required for this access but R/W is only needed by the system when there are external writable resources. Therefore in normal expanded modes, only the E clock is configured for its alternate bus control function and the other bits of port E are configured for general-purpose I/O. If the normal expanded system needs any other bus-control signals, PEAR would need to be written before any access that needed the additional signals. In special expanded modes, IPIPE1, IPIPE0, E, R/W, and LSTRB are configured as bus-control signals. In peripheral mode, the PEAR register is not accessible for reads or writes. NDBE -- No Data Bus Enable Read and write anytime. 0 = PE7 is used for external control of data enables on memories. 1 = PE7 is used for general-purpose I/O. PIPOE -- Pipe Signal Output Enable Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in single chip modes. 0 = PE[6:5] are general-purpose I/O. 1 = PE[6:5] are outputs and indicate the state of the instruction queue. NECLK -- No External E Clock In expanded modes, writes to this bit have no effect. E clock is required for de-multiplexing the external address; NECLK will remain zero in expanded modes. NECLK can be written once in normal singlechip mode and can be written anytime in special single chip mode. The bit can be read anytime. 0 = PE4 is the external E-clock pin subject to the following limitation: In single-chip modes, PE4 is general-purpose I/O unless NECLK = 0 and either IVIS = 1 or ESTR = 0. A 16-bit write to PEAR:MODE can configure all three bits in one operation. 1 = PE4 is a general-purpose I/O pin. LSTRE -- Low Strobe (LSTRB) Enable Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in single-chip modes or normal expanded narrow mode. 0 = PE3 is a general-purpose I/O pin. 1 = PE3 is configured as the LSTRB bus-control output, provided the MCU is not in single chip or normal expanded narrow modes. LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled. If needed, it should be enabled before external writes. External reads do not normally need LSTRB because all 16 data bits can be driven even if the MCU only needs eight bits of data. TAGLO is a shared function of the PE3/LSTRB pin. In special expanded modes with LSTRE set and the BDM instruction tagging on, a zero at the falling edge of E tags the instruction word low byte being read into the instruction queue. RDWE -- Read/Write Enable Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in single-chip modes. 0 = PE2 is a general-purpose I/O pin. 1 = PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a general-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed it should be enabled before any external writes.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 35
PUCR -- Pull-Up Control Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 PUPE 1 3 0 0 2 0 0 1 PUPB 0 Bit 0 PUPA 0
$000C
These bits select pull-up resistors for any pin in the corresponding port that is currently configured as an input. This register is not in the map in peripheral mode. Read and write anytime. PUPE -- Pull-Up Port E Enable Pin PE1 always has a pull-up. Pins PE6, PE5, and PE4 never have pull-ups. 0 = Port E pull-ups on PE7, PE3, PE2, and PE0 are disabled. 1 = Enable pull-up devices for port E input pins PE7, PE3, PE2, and PE0. PUPB -- Pull-Up Port B Enable 0 = Port B pull-ups are disabled. 1 = Enable pull-up devices for all port B input pins. This bit has no effect if port B is being used as part of the address/data bus (the pull-ups are inactive). PUPA -- Pull-Up Port A Enable 0 = Port A pull-ups are disabled. 1 = Enable pull-up devices for all port A input pins. This bit has no effect if port A is being used as part of the address/data bus (the pull-ups are inactive). RDRIV -- Reduced Drive of I/O Lines
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 RDPE 0 2 0 0 1 RDPB 0 Bit 0 RDPA 0
$000D
These bits select reduced drive for the associated port pins. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). The reduced drive function is independent of which function is being used on a particular port. This register is not in the map in peripheral mode. Normal: write once; Special: write anytime except the first time. Read anytime. RDPE -- Reduced Drive of Port E 0 = All port E output pins have full drive enabled. 1 = All port E output pins have reduced drive capability. RDPB -- Reduced Drive of Port B 0 = All port B output pins have full drive enabled. 1 = All port B output pins have reduced drive capability. RDPA -- Reduced Drive of Port A 0 = All port A output pins have full drive enabled. 1 = All port A output pins have reduced drive capability.
MOTOROLA 36
MC68HC912B32 MC68HC912B32TS/D
7 Flash EEPROM
The 32-Kbyte Flash EEPROM module for the MC68HC912B32 serves as electrically erasable and programmable, non-volatile ROM emulation memory. The module can be used for program code that must either execute at high speed or is frequently executed, such as operating system kernels and standard subroutines, or it can be used for static data which is read frequently. The Flash EEPROM is ideal for program storage for single-chip applications allowing for field reprogramming. 7.1 Overview The Flash EEPROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. The Flash EEPROM module requires an external program/erase voltage (VFP) to program or erase the Flash EEPROM array. The external program/erase voltage is provided to the Flash EEPROM module via an external VFP pin. To prevent damage to the flash array, VFP should always be greater than or equal to VDD-0.5V. Programming is by byte or aligned word. The Flash EEPROM module supports bulk erase only. The Flash EEPROM module has hardware interlocks which protect stored data from accidental corruption. An erase- and program-protected 2-Kbyte block for boot routines is located at $7800-$7FFF or $F800-$FFFF depending upon the mapped location of the Flash EEPROM array. (The protected boot block on the initial mask sets, G86W and G75R, is 1-Kbyte and is located at $7C00-$7FFF or $FC00- $FFFF.) 7.2 Flash EEPROM Control Block A 4-byte register block controls the Flash EEPROM module operation. Configuration information is specified and programmed independently from the contents of the Flash EEPROM array. At reset, the 4-byte register section starts at address $00F4. 7.3 Flash EEPROM Array After reset, the Flash EEPROM array is located from addresses $8000 to $FFFF in single-chip mode. In Expanded modes the Flash EEPROM array is located from address $0000 to $7FFF, however, it is turned off. The Flash EEPROM can be mapped to an alternate address range. See 5 Operating Modes and Resource Mapping. 7.4 Flash EEPROM Registers FEELCK -- Flash EEPROM Lock Control Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 LOCK 0
$00F4
In normal modes the LOCK bit can only be written once after reset. LOCK -- Lock Register Bit 0 = Enable write to FEEMCR register 1 = Disable write to FEEMCR register
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 37
FEEMCR -- Flash EEPROM Module Configuration Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 BOOTP 1
$00F5
This register controls the operation of the Flash EEPROM array. BOOTP cannot be changed when the LOCK control bit in the FEELCK register is set or if ENPE in the FEECTL register is set. BOOTP -- Boot Protect The boot block is located at $7800-$7FFF or $F800-$FFFF depending upon the mapped location of the Flash EEPROM array and mask set ($7C00-$7FFF or $FC00-$FFFF for 1-Kbyte block). 0 = Enable erase and program of 1-Kbyte or 2-Kbyte boot block 1 = Disable erase and program of 1-Kbyte or 2-Kbyte boot block FEETST -- Flash EEPROM Module Test Register
Bit 7 FSTE RESET: 0 6 GADR 0 5 HVT 0 4 FENLV 0 3 FDISVFP 0 2 VTCK 0 1 STRE 0 Bit 0 MWPR 0
$00F6
In normal mode, writes to FEETST control bits have no effect and always read zero. The Flash EEPROM module cannot be placed in test mode inadvertently during normal operation. FSTE -- Stress Test Enable 0 = Disables the gate/drain stress circuitry 1 = Enables the gate/drain stress circuitry GADR -- Gate/Drain Stress Test Select 0 = Selects the drain stress circuitry 1 = Selects the gate stress circuitry HVT -- Stress Test High Voltage Status 0 = High voltage not present during stress test 1 = High voltage present during stress test FENLV -- Enable Low Voltage 0 = Disables low voltage transistor in current reference circuit 1 = Enables low voltage transistor in current reference circuit FDISVFP -- Disable Status VFP Voltage Lock When the VFP pin is below normal programming voltage the Flash module will not allow writing to the LAT bit; the user cannot erase or program the Flash module. The FDISVFP control bit enables writing to the LAT bit regardless of the voltage on the VFP pin. 0 = Enable the automatic lock mechanism if VFP is low 1 = Disable the automatic lock mechanism if VFP is low VTCK -- VT Check Test Enable When VTCK is set, the Flash EEPROM module uses the VFP pin to control the control gate voltage; the sense amp time-out path is disabled. This allows for indirect measurements of the bit cells program and erase threshold. If VFP < VZBRK (breakdown voltage) the control gate will equal the VFP voltage. If VFP > VZBRK the control gate will be regulated by the following equation: Vcontrol gate = VZBRK + 0.44 x (VFP - VZBRK) 0 = VT test disable 1 = VT test enable
MOTOROLA 38
MC68HC912B32 MC68HC912B32TS/D
STRE -- Spare Test Row Enable The spare test row consists of one Flash EEPROM array row. The reserved word at location 31 contains production test information which must be maintained through several erase cycles. When STRE is set, the decoding for the spare test row overrides the address lines which normally select the other rows in the array. 0 = LIB accesses are to the Flash EEPROM array 1 = Spare test row in array enabled if SMOD is active MWPR -- Multiple Word Programming Used primarily for testing, if MPWR = 1, the two least-significant address lines ADDR[1:0] will be ignored when programming a Flash EEPROM location. The word location addressed if ADDR[1:0] = 00, along with the word location addressed if ADDR[1:0] = 10, will both be programmed with the same word data from the programming latches. This bit should not be changed during programming. 0 = Multiple word programming disabled 1 = Program 32 bits of data FEECTL -- Flash EEPROM Control Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 FEESWAI 0 3 SVFP 0 2 ERAS 0 1 LAT 0 Bit 0 ENPE 0
$00F7
This register controls the programming and erasure of the Flash EEPROM. FEESWAI -- Flash EEPROM Stop in Wait Control 0 = Do not halt Flash EEPROM clock when the part is in wait mode. 1 = Halt Flash EEPROM clock when the part is in wait mode. NOTE The FEESWAI bit cannot be asserted if the interrupt vector resides in theFlash EEPROM array. SVFP -- Status VFP Voltage SVFP is a read only bit. 0 = Voltage of VFP pin is below normal programming voltage levels 1 = Voltage of VFP pin is above normal programming voltage levels ERAS -- Erase Control This bit can be read anytime or written when ENPE = 0. When set, all locations in the array will be erased at the same time. The boot block will be erased only if BOOTP = 0. This bit also affects the result of attempted array reads. See Table 14 for more information. Status of ERAS cannot change if ENPE is set. 0 = Flash EEPROM configured for programming 1 = Flash EEPROM configured for erasure LAT -- Latch Control This bit can be read anytime or written when ENPE = 0. When set, the Flash EEPROM is configured for programming or erasure and, upon the next valid write to the array, the address and data will be latched for the programming sequence. See Table 14 for the effects of LAT on array reads. A high voltage detect circuit on the VFP pin will prevent assertion of the LAT bit when the programming voltage is at normal levels. 0 = Programming latches disabled 1 = Programming latches enabled
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 39
ENPE -- Enable Programming/Erase 0 = Disables program/erase voltage to Flash EEPROM 1 = Applies program/erase voltage to Flash EEPROM ENPE can be asserted only after LAT has been asserted and a write to the data and address latches has occurred. If an attempt is made to assert ENPE when LAT is negated, or if the latches have not been written to after LAT was asserted, ENPE will remain negated after the write cycle is complete. The LAT, ERAS and BOOTP bits cannot be changed when ENPE is asserted. A write to FEECTL may only affect the state of ENPE. Attempts to read a Flash EEPROM array location in the Flash EEPROM module while ENPE is asserted will not return the data addressed. See Table 14 for more information. Flash EEPROM module control registers may be read or written while ENPE is asserted. If ENPE is asserted and LAT is negated on the same write access, no programming or erasure will be performed. Table 14 Effects of ENPE, LAT and ERAS on Array Reads
ENPE 0 0 0 1 LAT 0 1 1 - ERAS - 0 1 - Result of Read Normal read of location addressed Read of location being programmed Normal read of location addressed Read cycle is ignored
7.5 Operation The Flash EEPROM can contain program and data. On reset, it can operate as a bootstrap memory to provide the CPU with internal initialization information during the reset sequence. 7.5.1 Bootstrap Operation Single-Chip Mode After reset, the CPU controlling the system will begin booting up by fetching the first program address from address $FFFE. 7.5.2 Normal Operation The Flash EEPROM allows a byte or aligned word read/write in one bus cycle. Misaligned word read/ write require an additional bus cycle. The Flash EEPROM array responds to read operations only. Write operations are ignored. 7.5.3 Program/Erase Operation An unprogrammed Flash EEPROM bit has a logic state of one. A bit must be programmed to change its state from one to zero. Erasing a bit returns it to a logic one. The Flash EEPROM has a minimum program/erase life of 100 cycles. Programming or erasing the Flash EEPROM is accomplished by a series of control register writes and a write to a set of programming latches. Programming is restricted to a single byte or aligned word at a time as determined by internal signal SZ8 and ADDR[0]. The Flash EEPROM must first be completely erased prior to programming final data values. It is possible to program a location in the Flash EEPROM without erasing the entire array if the new value does not require the changing of bit values from zero to one. Read/Write Accesses During Program/Erase -- During program or erase operations, read and write accesses may be different from those during normal operation and are affected by the state of the control bits in the Flash EEPROM control register (FEECTL). The next write to any valid address to the array after LAT is set will cause the address and data to be latched into the programming latches. Once the address and data are latched, write accesses to the array will be ignored while LAT is set. Writes to the control registers will occur normally. Program/Erase Verification -- When programming or erasing the Flash EEPROM array, a special verification method is required to ensure that the program/erase process is reliable, and also to provide
MOTOROLA 40
MC68HC912B32 MC68HC912B32TS/D
the longest possible life expectancy. This method requires stopping the program/erase sequence at periods of tPPULSE (tEPULSE for erasing) to determine if the Flash EEPROM is programmed/erased. After the location reaches the proper value, it must continue to be programmed/erased with additional margin pulses to ensure that it will remain programmed/erased. Failure to provide the margin pulses could lead to corrupted or unreliable data. Program/Erase Sequence -- To begin a program or erase sequence the external VFP voltage must be applied and stabilized. The ERAS bit must be set or cleared, depending on whether a program sequence or an erase sequence is to occur. The LAT bit will be set to cause any subsequent data written to a valid address within the Flash EEPROM to be latched into the programming address and data latches. The next Flash array write cycle must be either to the location that is to be programmed if a programming sequence is being performed, or, if erasing, to any valid Flash EEPROM array location. Writing the new address and data information to the Flash EEPROM is followed by assertion of ENPE to turn on the program/erase voltage to program/erase the new location(s). The LAT bit must be asserted and the address and data latched to allow the setting of the ENPE control bit. If the data and address have not been latched, an attempt to assert ENPE will be ignored and ENPE will remain negated after the write cycle to FEECTL is completed. The LAT bit must remain asserted and the ERAS bit must remain in its current state as long as ENPE is asserted. A write to the LAT bit to clear it while ENPE is set will be ignored. That is, after the write cycle, LAT will remain asserted. Likewise, an attempt to change the state of ERAS will be ignored and the state of the ERAS bit will remain unchanged. The programming software is responsible for all timing during a program sequence. This includes the total number of program pulses (nPP), the length of the program pulse (tPPULSE), the program margin pulses (pm) and the delay between turning off the high voltage and verifying the operation (tVPROG). The erase software is responsible for all timing during an erase sequence. This includes the total number of erase pulses (em), the length of the erase pulse (tEPULSE), the erase margin pulse or pulses, and the delay between turning off the high voltage and verifying the operation (tVERASE). Software also controls the supply of the proper program/erase voltage to the VFP pin, and should be at the proper level before ENPE is set during a program/erase sequence. A program/erase cycle should not be in progress when starting another program/erase, or while attempting to read from the array. NOTE Although clearing ENPE disables the program/erase voltage (VFP) from the VFP pin to the array, care must be taken to ensure that VFP is at VDD whenever programming/erasing is not in progress. Not doing so could damage the part. Ensuring that VFP is always greater or equal to VDD can be accomplished by controlling the VFP power supply with the programming software via an output pin. Alternatively, all programming and erasing can be done prior to installing the device on an application circuit board which can always connect VFP to VDD. Programming can also be accomplished by plugging the board into a special programming fixture which provides program/erase voltage to the VFP pin.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 41
7.6 Programming the Flash EEPROM Programming the Flash EEPROM is accomplished by the following sequence. The VFP pin voltage must be at the proper level prior to executing step 4 the first time. 1. Apply program/erase voltage to the VFP pin. 2. Clear ERAS and set the LAT bit in the FEECTL register to establish program mode and enable programming address and data latches. 3. Write data to a valid address. The address and data is latched. If BOOTP is asserted, an attempt to program an address in the boot block will be ignored. 4. Apply programming voltage by setting ENPE. 5. Delay for one programming pulse (tPPULSE). 6. Remove programming voltage by clearing ENPE. 7. Delay while high voltage is turning off (tVPROG). 8. Read the address location to verify that it has been programmed * If the location is not programmed, repeat steps 4 through 7 until the location is programmed or until the specified maximum number of program pulses has been reached (nPP) * If the location is programmed, repeat the same number of pulses as required to program the location. This provides 100% program margin. 9. Read the address location to verify that it remains programmed. 10. Clear LAT. 11. If there are more locations to program, repeat steps 2 through 10. 12. Turn off VFP (reduce voltage on VFP pin to VDD). The flowchart in Figure 7 demonstrates the recommended programming sequence.
MOTOROLA 42
MC68HC912B32 MC68HC912B32TS/D
START PROG TURN ON VFP CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER (nPP)
CLEAR ERAS SET LAT
WRITE DATA TO ADDRESS
SET ENPE DELAY FOR DURATION OF PROGRAM PULSE (tPPULSE)
CLEAR ENPE DELAY BEFORE VERIFY (tVPROG) INCREMENT nPP COUNTER READ LOCATION SET MARGIN FLAG
IS MARGIN FLAG SET? YES DECREMENT nPP COUNTER
NO
DATA CORRECT? NO
YES
NO
nPP = 0? YES DATA CORRECT? YES CLEAR LAT LOCATION FAILED TO PROGRAM nPP = 50? NO YES NO
GET NEXT ADDRESS/DATA
NO
DONE? YES TURN OFF VFP
DONE PROG
Figure 7 Program Sequence Flow
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 43
7.7 Erasing the Flash EEPROM The following sequence demonstrates the recommended procedure for erasing the Flash EEPROM. The VFP pin voltage must be at the proper level prior to executing step 4 the first time. 1. Turn on VFP (apply program/erase voltage to the VFP pin). 2. Set the LAT bit and ERAS bit to configure the Flash EEPROM for erasing. 3. Write to any valid address in the Flash array. This allows the erase voltage to be turned on; the data written and the address written are not important. The boot block will be erased only if the control bit BOOTP is negated. 4. Apply erase voltage by setting ENPE. 5. Delay for a single erase pulse (tEPULSE). 6. Remove erase voltage by clearing ENPE. 7. Delay while high voltage is turning off (tVERASE). 8. Read the entire array to ensure that the Flash EEPROM is erased. * If all of the Flash EEPROM locations are not erased, repeat steps 4 through 7 until either the remaining locations are erased, or until the maximum erase pulses have been applied (nEP) * If all of the Flash EEPROM locations are erased, repeat the same number of pulses as required to erase the array. This provides 100% erase margin. 9. Read the entire array to ensure that the Flash EEPROM is erased. 10. Clear LAT. 11. Turn off VFP (reduce voltage on VFP pin to VDD). The flowchart in Figure 8 demonstrates the recommended erase sequence.
MOTOROLA 44
MC68HC912B32 MC68HC912B32TS/D
START ERASE TURN ON VFP CLEAR MARGIN FLAG CLEAR ERASE PULSE COUNTER (nEP)
SET ERAS SET LAT
WRITE TO ARRAY
SET ENPE DELAY FOR DURATION OF ERASE PULSE (tEPULSE)
CLEAR ENPE DELAY BEFORE VERIFY (tVERASE) INCREMENT nEP COUNTER READ ARRAY SET MARGIN FLAG
IS MARGIN FLAG SET? YES DECREMENT nEP COUNTER
NO
ARRAY ERASED? NO
YES
NO
nEP = 0? YES ARRAY ERASED? YES CLEAR LAT
nEP = 5? NO YES
NO
TURN OFF VFP
ARRAY ERASED
ARRAY FAILED TO ERASE
Figure 8 Erase Sequence Flow
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 45
7.8 Program/Erase Protection Interlocks The Flash EEPROM program and erase mechanisms provide maximum protection from accidental programming or erasure. The voltage required to program/erase the Flash EEPROM (VFP) is supplied via an external pin. If VFP is not present, no programming/erasing will occur. Furthermore, the program/erase voltage will not be applied to the Flash EEPROM unless turned on by setting a control bit (ENPE). The ENPE bit may not be set unless the programming address and data latches have been written previously with a valid address. The latches may not be written unless enabled by setting a control bit (LAT). The LAT and ENPE control bits must be written on separate writes to the control register (FEECTL) and must be separated by a write to the programming latches. The ERAS and LAT bits are also protected when ENPE is set. This prevents inadvertent switching between erase/program mode and also prevents the latched data and address from being changed after a program cycle has been initiated. 7.9 Stop or Wait Mode When stop or wait commands are executed, the MCU puts the Flash EEPROM in stop or wait mode. In these modes the Flash module will cease erasure or programming immediately. It is advised not to enter stop or wait modes when programming the Flash array. CAUTION The Flash EEPROM module is not able to recover from STOP without a 1 microsecond delay. This cannot be controlled internal to the MCU. Therefore, do not attempt to recover from STOP with an interrupt. Use RESET to recover from a STOP mode executed from Flash EEPROM. Recovery from a STOP instruction executed from EEPROM and RAM operate normally. 7.10 Test Mode The Flash EEPROM has some special test functions which are only accessible when the device is in test mode. Test mode is indicated to the Flash EEPROM module when the SMOD line on the LIB is asserted. When SMOD is asserted, the special test control bits may be accessed via the LIB to invoke the special test functions in the Flash EEPROM module. When SMOD is not asserted, writes to the test control bits have no effect and all bits in the test register FEETST will be cleared. This ensures that Flash EEPROM test mode cannot be invoked inadvertently during normal operation. Note that the Flash EEPROM module will operate normally, even if SMOD is asserted, until a special test function is invoked. The test mode adds additional features over normal mode which allow the tests to be performed even after the device is installed in the final product.
MOTOROLA 46
MC68HC912B32 MC68HC912B32TS/D
8 EEPROM
The MC68HC912B32 EEPROM serves as a 768-byte nonvolatile memory which can be used for frequently accessed static data or as fast access program code. The MC68HC912B32 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words or misaligned words. Access times is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. Programming is by byte or aligned word. Attempts to program or erase misaligned words will fail. Only the lower byte will be latched and programmed or erased. Programming and erasing of the user EEPROM can be done in all operating modes. Each EEPROM byte or aligned word must be erased before programming. The EEPROM module supports byte, aligned word, row (32 bytes) or bulk erase, all using the internal charge pump. Bulk erasure of odd and even rows is also possible in test modes; the erased state is $FF. The EEPROM module has hardware interlocks which protect stored data from corruption by accidentally enabling the program/ erase voltage. Programming voltage is derived from the internal VDD supply with an internal charge pump. The EEPROM has a minimum program/erase life of 10,000 cycles over the complete operating temperature range. 8.1 EEPROM Programmer's Model The EEPROM module consists of two separately addressable sections. The first is a four-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array itself. At reset, the four-byte register section starts at address $00F0 and the EEPROM array is located from addresses $0D00 to $0FFF (see Figure 9). For information on remapping the register block and EEPROM address space, refer to 5 Operating Modes and Resource Mapping. Read access to the memory array section can be enabled or disabled by the EEON control bit in the INITEE register. This feature allows the access of memory mapped resources that have lower priority than the EEPROM memory array. EEPROM control registers can be accessed and EEPROM locations may be programmed or erased regardless of the state of EEON. Using the normal EEPROG control, it is possible to continue program/erase operations during WAIT. For lowest power consumption during WAIT, stop program/erase by turning off EEPGM. If the STOP mode is entered during programming or erasing, program/erase voltage will be automatically turned off and the RC clock (if enabled) is stopped. However, the EEPGM control bit will remain set. When STOP mode is terminated, the program/erase voltage will be automatically turned back on if EEPGM is set. At bus frequencies below 1 MHz, the RC clock must be turned on for program/erase.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 47
$_D00
BPROT4 (256 BYTES)
$_E00 BPROT3 (256 BYTES)
SINGLE CHIP VECTORS $FF80 RESERVED (64 BYTES)
$_F00 BPROT2 (128 BYTES) $_F80 $_FC0 BPROT1 BPROT0
$FFBF $FFC0 VECTORS (64 BYTES) $FFFF
HC912B32 EEPROM BLOCK PROT
Figure 9 EEPROM Block Protect Mapping 8.2 EEPROM Control Registers EEMCR -- EEPROM Module Configuration
Bit 7 1 RESET: 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 Bit 0 EERC 0
$00F0
EESWAI PROTLCK 1 0
EESWAI -- EEPROM Stops in Wait Mode 0 = Module is not affected during wait mode 1 = Module ceases to be clocked during wait mode This bit should be cleared if the wait mode vectors are mapped in the EEPROM array. PROTLCK -- Block Protect Write Lock 0 = Block protect bits and bulk erase protection bit can be written 1 = Block protect bits are locked Read anytime. Write once in normal modes (SMODN = 1), set and clear any time in special modes (SMODN = 0). EERC -- EEPROM Charge Pump Clock 0 = System clock is used as clock source for the internal charge pump. Internal RC oscillator is stopped. 1 = Internal RC oscillator drives the charge pump. The RC oscillator is required when the system bus clock is lower than fPROG. Read and write anytime. EEPROT -- EEPROM Block Protect
Bit 7 1 RESET: 1 6 1 1 5 1 1 4 BPROT4 1 3 BPROT3 1 2 BPROT2 1 1 BPROT1 1 Bit 0 BPROT0 1
$00F1
Prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0.
MOTOROLA 48
MC68HC912B32 MC68HC912B32TS/D
BPROT[4:0] -- EEPROM Block Protection 0 = Associated EEPROM block can be programmed and erased. 1 = Associated EEPROM block is protected from being programmed and erased. Cannot be modified while programming is taking place (EEPGM = 1). Table 15 768-Byte EEPROM Block Protection
Bit Name BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 Block Protected $0D00 to $0DFF $0E00 to $0EFF $0F00 to $0F7F $0F80 to $0FBF $0FC0 to $0FFF Block Size 256 Bytes 256 Bytes 128 Bytes 64 Bytes 64 Bytes
EETST -- EEPROM Test
Bit 7 EEODD RESET: 0 6 EEVEN 0 5 MARG 0 4 EECPD 0 3 EECPRD 0 2 0 0 1 EECPM 0 Bit 0 0 0
$00F2
Read anytime. Write in special modes only (SMODN = 0). These bits are used for test purposes only. In normal modes the bits are forced to zero. EEODD -- Odd Row Programming 0 = Odd row bulk programming/erasing is disabled. 1 = Bulk program/erase all odd rows. Refers to a physical location in the array rather than an odd byte address. EEVEN -- Even Row Programming 0 = Even row bulk programming/erasing is disabled. 1 = Bulk program/erase all even rows. Refers to a physical location in the array rather than an even byte address. MARG -- Program and Erase Voltage Margin Test Enable 0 = Normal operation. 1 = Program and erase margin test. This bit is used to evaluate the program/erase voltage margin. EECPD -- Charge Pump Disable 0 = Charge pump is turned on during program/erase. 1 = Disable charge pump. EECPRD -- Charge Pump Ramp Disable Known to enhance write/erase endurance of EEPROM cells. 0 = Charge pump is turned on progressively during program/erase. 1 = Disable charge pump controlled ramp up. EECPM -- Charge Pump Monitor Enable 0 = Normal operation. 1 = Output the charge pump voltage on the IRQ/VPP pin.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 49
EEPROG -- EEPROM Control
Bit 7 BULKP RESET: 1 6 0 0 5 0 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 Bit 0 EEPGM 0
$00F3
BULKP -- Bulk Erase Protection 0 = EEPROM can be bulk erased. 1 = EEPROM is protected from being bulk or row erased. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. BYTE -- Byte and Aligned Word Erase 0 = Bulk or row erase is enabled. 1 = One byte or one aligned word erase only. Read anytime. Write anytime if EEPGM = 0. ROW -- Row or Bulk Erase (when BYTE = 0) 0 = Erase entire EEPROM array. 1 = Erase only one 32-byte row. Read anytime. Write anytime if EEPGM = 0. BYTE and ROW have no effect when ERASE = 0 Table 16 Erase Selection
BYTE 0 0 1 1 ROW 0 1 0 1 Block Size Bulk erase entire EEPROM array Row erase 32 bytes Byte or aligned word erase Byte or aligned word erase
If BYTE = 1 and test mode is not enabled, only the location specified by the address written to the programming latches will be erased. The operation will be a byte or an aligned word erase depending on the size of written data. ERASE -- Erase Control 0 = EEPROM configuration for programming or reading. 1 = EEPROM configuration for erasure. Read anytime. Write anytime if EEPGM = 0. Configures the EEPROM for erasure or programming. When test mode is not enabled and unless BULKP is set, erasure is by byte, aligned word, row or bulk. EELAT -- EEPROM Latch Control 0 = EEPROM set up for normal reads. 1 = EEPROM address and data bus latches set up for programming or erasing. Read anytime. Write anytime if EEPGM = 0. BYTE, ROW, ERASE and EELAT bits can be written simultaneously or in any sequence. EEPGM -- Program and Erase Enable 0 = Disables program/erase voltage to EEPROM. 1 = Applies program/erase voltage to EEPROM. The EEPGM bit can be set only after EELAT has been set. When an attempt is made to set EELAT and EEPGM simultaneously, EEPGM remains clear but EELAT is set. The BULKP, BYTE, ROW, ERASE and EELAT bits cannot be changed when EEPGM is set. To complete a program or erase, two successive writes to clear EEPGM and EELAT bits are required before reading the programmed data. A write to an EEPROM location has no effect when EEPGM is set. Latched address and data cannot be modified during program or erase.
MOTOROLA 50
MC68HC912B32 MC68HC912B32TS/D
A program or erase operation should follow the sequence below: 1. 2. 3. 4. 5. 6. Write BYTE, ROW and ERASE to the desired value; write EELAT = 1 Write a byte or an aligned word to an EEPROM address Write EEPGM = 1 Wait for programming (tPROG) or erase (tERASE) delay time Write EEPGM = 0 Write EELAT = 0
It is possible to program/erase more bytes or words without intermediate EEPROM reads, by jumping from step 5 to step 2.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 51
9 Resets and Interrupts
CPU12 exceptions include resets and interrupts. Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the exception is located. Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and non-maskable interrupt sources. The remainder of the vectors are used for maskable interrupts, and all must be initialized to point to the address of the appropriate service routine. 9.1 Exception Priority A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are not maskable. The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. The priorities of the non-maskable sources are: 1. 2. 3. 4. 5. 6. POR or RESET pin Clock monitor reset COP watchdog reset Unimplemented instruction trap Software interrupt instruction (SWI) XIRQ signal (if X bit in CCR = 0)
9.2 Maskable Interrupts Maskable interrupt sources include on-chip peripheral systems and external interrupt service requests. Interrupts from these sources are recognized when the global interrupt mask bit (I) in the CCR is cleared. The default state of the I bit out of reset is one, but it can be written at any time. Interrupt sources are prioritized by default but any one maskable interrupt source may be assigned the highest priority by means of the HPRIO register. The relative priorities of the other sources remain the same. An interrupt that is assigned highest priority is still subject to global masking by the I bit in the CCR, or by any associated local bits. Interrupt vectors are not affected by priority assignment. HPRIO can only be written while the I bit is set (interrupts inhibited). Table 17 lists interrupt sources and vectors in default order of priority. Table 17 Interrupt Vector Map
Vector Address $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB Reset COP clock monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real time interrupt Timer channel 0 Timer channel 1 Timer channel 2 Interrupt Source CCR Mask None None None None None X bit I bit I bit I bit I bit I bit Local Enable Register (Bit) None COPCTL (CME, FCME) COP rate selected None None None INTCR (IRQEN) RTICTL (RTIE) TMSK1 (C0I) TMSK1 (C1I) TMSK1 (C2I) HPRIO Value to Elevate - - - - - - $F2 $F0 $EE $EC $EA
MOTOROLA 52
MC68HC912B32 MC68HC912B32TS/D
Table 17 Interrupt Vector Map
Vector Address $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FF80-$FFCF Interrupt Source Timer channel 3 Timer channel 4 Timer channel 5 Timer channel 6 Timer channel 7 Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI serial transfer complete SCI 0 Reserved ATD BDLC Reserved CCR Mask I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit Local Enable Register (Bit) TMSK1 (C3I) TMSK1 (C4I) TMSK1 (C5I) TMSK1 (C6I) TMSK1 (C7I) TMSK2 (TOI) PACTL (PAOVI) PACTL (PAI) SP0CR1 (SPIE) SC0CR2 (TIE, TCIE, RIE, ILIE) - ATDCTL2 (ASCIE) BCR1 (IE) - HPRIO Value to Elevate $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $D0 $80-$CE
9.3 Interrupt Control and Priority Registers INTCR -- Interrupt Control Register
Bit 7 IRQE RESET: 0 6 IRQEN 1 5 DLY 1 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$001E
IRQE -- IRQ Select Edge Sensitive Only 0 = IRQ configured for low-level recognition. 1 = IRQ configured to respond only to falling edges (on pin PE1/IRQ). IRQE can be read anytime and written once in normal modes. In special modes, IRQE can be read anytime and written anytime, except the first write is ignored. IRQEN -- External IRQ Enable The IRQ pin has an internal pull-up. 0 = External IRQ pin disconnected from interrupt logic 1 = External IRQ pin connected to interrupt logic IRQEN can be read and written anytime in all modes. DLY -- Enable Oscillator Start-Up Delay on Exit from STOP The delay time of about 4096 cycles is based on the E clock rate. 0 = No stabilization delay imposed on exit from STOP mode. A stable external oscillator must be supplied. 1 = Stabilization delay is imposed before processing resumes after STOP. DLY can be read anytime and written once in normal modes. In special modes, DLY can be read and written anytime.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 53
HPRIO -- Highest Priority I Interrupt
Bit 7 1 RESET: 1 6 1 1 5 PSEL5 1 4 PSEL4 1 3 PSEL3 0 2 PSEL2 0 1 PSEL1 1 Bit 0 0 0
$001F
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime. To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO register. For example, writing $F0 to HPRIO would assign highest maskable interrupt priority to the real-time interrupt timer ($FFF0). If an unimplemented vector address or a non-I-masked vector address (value higher than $F2) is written, then IRQ will be the default highest priority interrupt. 9.4 Resets There are four possible sources of reset. Power-on reset (POR), and external reset on the RESET pin share the normal reset vector. The computer operating properly (COP) reset and the clock monitor reset each has a vector. Entry into reset is asynchronous and does not require a clock but the MCU cannot sequence out of reset without a system clock. 9.4.1 Power-On Reset A positive transition on VDD causes a power-on reset (POR). An external voltage level detector, or other external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. 9.4.2 External Reset The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than eight E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then released. Eight E-clock cycles later it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor. To prevent a COP or clock monitor reset from being detected during an external reset, hold the reset pin low for at least 32 cycles. An external RC power-up delay circuit on the reset pin is not recommended -- circuit charge time can cause the MCU to misinterpret the type of reset that has occurred. 9.4.3 COP Reset The MCU includes a computer operating properly (COP) system to help protect against software failures. When COP is enabled, software must write $55 and $AA (in this order) to the COPRST register in order to keep a watchdog timer from timing out. Other instructions may be executed between these writes. A write of any value other than $55 or $AA or software failing to execute the sequence properly causes a COP reset to occur. 9.4.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 9.5 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states, as follows. 9.5.1 Operating Mode and Memory Map Operating mode and default memory mapping are determined by the states of the BKGD, MODA, and MODB pins during reset. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset. Operating mode and default maps can subsequently be changed according to strictly defined rules.
MOTOROLA 54
MC68HC912B32 MC68HC912B32TS/D
9.5.2 Clock and Watchdog Control Logic The COP watchdog system is enabled, with the CR[2:0] bits set for the shortest duration time-out. The clock monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The rate control bits are cleared, and must be initialized before the RTI system is used. The DLY control bit is set to specify an oscillator start-up delay upon recovery from STOP mode. 9.5.3 Interrupts PSEL is initialized in the HPRIO register with the value $F2, causing the external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR systems). However, the interrupt mask bits in the CPU12 CCR are set to mask X and I related interrupt requests. 9.5.4 Parallel I/O If the MCU comes out of reset in an expanded mode, port A and port B are used for the multiplexed address/data bus and port E pins are normally used to control the external bus (operation of port E pins can be affected by the PEAR register). If the MCU comes out of reset in a single-chip mode, all ports are configured as general-purpose high-impedance inputs. Port S, port T, port DLC, port P, and port AD are all configured as general-purpose inputs. 9.5.5 Central Processing Unit After reset, the CPU fetches a vector from the appropriate address, then begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after reset. The CCR X and I interrupt mask bits are set to mask any interrupt requests. The S bit is also set to inhibit the STOP instruction. 9.5.6 Memory After reset, the internal register block is located at $0000-$01FF, the register-following space is at $0200-$03FF, and RAM is at $0800-$0BFF. EEPROM is located at $0D00-$0FFF. Flash EEPROM is located at $8000-$FFFF in single-chip modes and at $0000-$7FFF (but disabled) in expanded modes. 9.5.7 Other Resources The timer, serial communications interface (SCI), serial peripheral interface (SPI), byte data link controller (BDLC), pulse-width modulator (PWM), and analog-to-digital converter (ATD) are off after reset. 9.6 Register Stacking Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared. When an interrupt service request is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the instruction. Some of the longer instructions can be interrupted and will resume normally after servicing the interrupt. When the CPU begins to service an interrupt, the instruction queue is cleared, the return address is calculated, and then it and the contents of the CPU registers are stacked as shown in Table 18. Table 18 Stacking Order on Entry to Interrupts
Memory Location SP - 2 SP - 4 SP - 6 SP - 8 SP - 9 CPU Registers RTNH : RTNL YH : YL XH : XL B:A CCR
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 55
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service request is pending) is set to prevent other interrupts from disrupting the interrupt service routine. The interrupt vector for the highest priority source that was pending at the beginning of the interrupt sequence is fetched, and execution continues at the referenced location. At the end of the interrupt service routine, an RTI instruction restores the content of all registers from information on the stack, and normal program execution resumes. If another interrupt is pending at the end of an interrupt service routine, the register unstacking and restacking is bypassed and the vector of the pending interrupt is fetched.
MOTOROLA 56
MC68HC912B32 MC68HC912B32TS/D
10 Clock Functions
Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MC68HC912B32. 10.1 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. The MCU uses three types of internal clock signals derived from the primary clock signal: T clocks, E clock, and P clock. The T clocks are used by the CPU. The E and P clocks are used by the bus interfaces, BDM, SPI, and ATD. The P clock also drives on-chip modules such as the timer chain, SCI, RTI, COP, and restart-fromstop delay time. Figure 10 shows clock timing relationships.
T1CLK T2CLK T3CLK T4CLK INT ECLK PCLK
HC12B32 CLOCK RELATIONS
Figure 10 Internal Clock Relationships 10.2 Computer Operating Properly (COP) The COP or watchdog timer is an added check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping a free-running watchdog timer from timing out. If the watchdog timer times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated. Three control bits allow selection of seven COP time-out periods or COP disable. When COP is enabled, sometime during the selected period the program must write $55 and $AA (in this order) to the COPRST register. If the program fails to do this the part will reset. If any value other than $55 or $AA is written to COPRST, the part is reset. 10.3 Real-Time Interrupt There is a real-time (periodic) interrupt available to the user. This interrupt will occur at one of seven selected rates. An interrupt flag and an interrupt enable bit are associated with this function. There are three bits for the rate select. 10.4 Clock Monitor The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay. If no MCU clock edges are detected within this RC time delay, the clock monitor can optionally generate a system reset. The clock monitor function is enabled/disabled by the CME control bit in the COPCTL register. This time-out is based on an RC delay so that the clock monitor can operate without any MCU clocks. Clock monitor time-outs are shown in Table 19.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 57
Table 19 Clock Monitor Time-Outs
Supply 5V +/- 10% 3V +/- 10% Range 2-20 S 5-100 S
10.5 Clock Function Registers All register addresses shown reflect the reset state. Registers may be mapped to any 2-Kbyte space. RTICTL -- Real-Time Interrupt Control Register
Bit 7 RTIE RESET: 0 6 RSWAI 0 5 RSBCK 0 4 0 0 3 RTBYP 0 2 RTR2 0 1 RTR1 0 Bit 0 RTR0 0
$0014
RTIE -- Real-Time Interrupt Enable Read and write anytime. 0 = Interrupt requests from RTI are disabled. 1 = Interrupt will be requested whenever RTIF is set. RSWAI -- RTI and COP Stop While in Wait Write once in normal modes, anytime in special modes. Read anytime. 0 = Allows the RTI and COP to continue running in wait. 1 = Disables both the RTI and COP whenever the part goes into wait. RSBCK -- RTI and COP Stop While in Background Debug Mode Write once in normal modes, anytime in special modes. Read anytime. 0 = Allows the RTI and COP to continue running while in background mode. 1 = Disables both the RTI and COP whenever the part is in background mode. This is useful for emulation. RTBYP -- Real-Time Interrupt Divider Chain Bypass Write not allowed in normal modes, anytime in special modes. Read anytime. 0 = Divider chain functions normally. 1 = Divider chain is bypassed, allows faster testing (the divider chain is normally P divided by 213, when bypassed becomes P divided by 4). RTR2, RTR1, RTR0 -- Real-Time Interrupt Rate Select Read and write anytime. Rate select for real-time interrupt. The clock used for this module is the E clock. Table 20 Real-Time Interrupt Rates
RTR2 0 0 0 0 1 1 1 1 RTR1 0 0 1 1 0 0 1 1 RTR0 0 1 0 1 0 1 0 1 Divide E By: OFF 213 214 215 216 217 218 219 Time-Out Period E = 4.0 MHz OFF 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms 131.72 ms Time-Out Period E = 8.0 MHz OFF 1.024 ms 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms
MOTOROLA 58
MC68HC912B32 MC68HC912B32TS/D
RTIFLG -- Real-Time Interrupt Flag Register
Bit 7 RTIF RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$0015
RTIF -- Real-Time Interrupt Flag This bit is cleared automatically by a write to this register with this bit set. 0 = Time-out has not yet occurred. 1 = Set when the time-out period is met. COPCTL -- COP Control Register
Bit 7 CME RESET: RESET: 0 0 6 FCME 0 0 5 FCM 0 0 4 FCOP 0 0 3 DISR 0 1 2 CR2 0 0 1 CR1 0 0 Bit 0 CR0 1 1 Normal Special
$0016
CME -- Clock Monitor Enable Read and write anytime. If FCME is set, this bit has no meaning nor effect. 0 = Clock monitor is disabled. Slow clocks and stop instruction may be used. 1 = Slow or stopped clocks (including the stop instruction) will cause a clock reset sequence. FCME -- Force Clock Monitor Enable Write once in normal modes, anytime in special modes. Read anytime. In normal modes, when this bit is set, the clock monitor function cannot be disabled until a reset occurs. 0 = Clock monitor follows the state of the CME bit. 1 = Slow or stopped clocks will cause a clock reset sequence. In order to use both STOP and clock monitor, the CME bit should be cleared prior to executing a STOP instruction and set after recovery from STOP. If you plan on using STOP always keep FCME = 0. FCM -- Force Clock Monitor Reset Writes are not allowed in normal modes, anytime in special modes. Read anytime. If DISR is set, this bit has no effect. 0 = Normal operation. 1 = Force a clock monitor reset (if clock monitor is enabled). FCOP -- Force COP Watchdog Reset Writes are not allowed in normal modes; can be written anytime in special modes. Read anytime. If DISR is set, this bit has no effect. 0 = Normal operation. 1 = Force a COP reset (if COP is enabled). DISR -- Disable Resets from COP Watchdog and Clock Monitor Writes are not allowed in normal modes, anytime in special modes. Read anytime. 0 = Normal operation. 1 = Regardless of other control bit states, COP and clock monitor will not generate a system reset. CR2, CR1, CR0 -- COP Watchdog Timer Rate Select Bits The COP system is driven by a constant frequency of E/213. (RTBYP in the RTICTL register allows all but two stages of this divider to be bypassed for testing in special modes only.) These bits specify an additional division factor to arrive at the COP time-out rate (the clock used for this module is the E clock). Write once in normal modes, anytime in special modes. Read anytime.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 59
Table 21 COP Watchdog Rates (RTBYP = 0)
CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 Divide E By: OFF 213 215 217 219 221 222 223 At E = 4.0 MHz Time-Out -0 to +2.048 ms OFF 2.048 ms 8.1920 ms 32.768 ms 131.072 ms 524.288 ms 1.048 s 2.097 s At E = 8.0 MHz Time-Out -0 to +1.024 ms OFF 1.024 ms 4.096 ms 16.384 ms 65.536 ms 262.144 ms 524.288 ms 1.048576 s
COPRST -- Arm/Reset COP Timer Register
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0017
Always reads $00. Writing $55 to this address is the first step of the COP watchdog sequence. Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may be executed between these writes but both must be completed in the correct order prior to time-out to avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur. 10.6 Clock Divider Chains Figure 11, Figure 12, Figure 13, and Figure 14 summarize the clock divider chains for the various peripherals on the MC68HC912B32.
TCLKs
EXTAL OSCILLATOR AND CLOCK GENERATOR XTAL SYSCLK
T CLOCK GENERATOR
TO CPU
/2
E AND P CLOCK ECLK GENERATOR PCLK TO BDM, BUSES, SPI, ATD, SCI, TIM, PULSE ACC, RTI, COP, PWM, BDLC
HC912B32 CLOCK DIV CHAIN
Figure 11 Clock Divider Chain
MOTOROLA 60
MC68HC912B32 MC68HC912B32TS/D
/ 22
/ 211
REGISTER: RTICTL BIT: RTBYP
0:0:0 REGISTER: RTICTL BITS: RTR2, RTR1, RTR0 REGISTER: BCR1 BITS: R1, R0 0:0 0:0:1
REGISTER: COPCTL BITS: CR2, CR1, CR0
0:0:0
0:0:1
/2
PCLK SC0BD MODULUS DIVIDER: / 1, 2, 3, 4, 5, 6, ..., 8190, 8191
0:1 1:0
/2 /2 /2 /2 /2 /2
0:1:0
/4 /4 /4 /4 /2 /2
0:1:0
/2 /2
0:1:1
0:1:1
1:1
1:0:0
1:0:0
1:0:1
1:0:1
1:1:0
1:1:0
SCI0 RECEIVE BAUD RATE ((16x)
/ 24
SCI0 TRANSMIT BAUD RATE (1x) TO BDLC
1:1:1
1:1:1
TO RTI
TO COP
HC912B32 CLOCK CHAIN SCI BDLC RTI COP
Figure 12 Clock Chain for SCI, BDLC, RTI, COP
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 61
PCLK TEN REGISTER: TMSK2 BITS: PR2, PR1, PR0 0:0:0 REGISTER: PACTL BITS: PAEN, CLK1, CLK0 0:x:x
/2 /2 /2 /2 /2 /2
PORT T7 PAEN
0:0:1
1:0:0
0:1:0
1:0:1
0:1:1 PULSE ACC LOW BYTE PACLK/256
1:1:0
1:0:0
1:1:1 PACLK/65536 (PAOV)
1:0:1 PULSE ACC HIGH BYTE TO TIM COUNTER
HC12 CLOCK CHAIN TIM
PACLK GATE LOGIC PAMOD
Figure 13 Clock Chain for TIM
PCLK
5-BIT MODULUS COUNTER (PR0-PR4)
/2
TO ATD
/2
REGISTER: SP0BR BITS: SPR2, SPR1, SPR0 0:0:0 SPI BIT RATE 0:0:1
/2 /2 /2 /2 /2 /2 /2
0:1:0
0:1:1 ECLK 1:0:0 SYNCHRONIZER 1:0:1 BKGD DIRECTION BKGD PIN LOGIC BKGD IN
BDM BIT CLOCK: Receive: Detect falling edge, count 12 E clocks, Sample input Transmit 1: Detect falling edge, count 6 E clocks while output is high impedance, drive out 1 E cycle pulse high, high impedance output again Transmit 0: Detect falling edge, drive out low, count 9 E clocks, drive out 1 E cycle pulse high, high impedance output
HC12 CLOCK CHAIN SPI ATD BDM
1:1:0
1:1:1
BKGD OUT
Figure 14 Clock Chain for SPI, ATD and BDM
MOTOROLA 62
MC68HC912B32 MC68HC912B32TS/D
11 Pulse-Width Modulator
The pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a combination of one 16-bit and two 8-bit PWM waveforms. Each waveform channel has a programmable period and a programmable duty-cycle as well as a dedicated counter. A flexible clock select scheme allows four different clock sources to be used with the counters. Each of the modulators can create independent, continuous waveforms with software-selectable duty rates from 0 percent to 100 percent. The PWM outputs can be programmed as left-aligned outputs or centeraligned outputs. The period and duty registers are double buffered so that if they change while the channel is enabled, the change will not take effect until the counter rolls over or the channel is disabled. If the channel is not enabled, then writes to the period and/or duty register will go directly to the latches as well as the buffer, thus ensuring that the PWM output will always be either the old waveform or the new waveform, not some variation in between. A change in duty or period can be forced into immediate effect by writing the new value to the duty and/ or period registers and then writing to the counter. This causes the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable it is possible to know where the count is with respect to the duty value and software can be used to make adjustments by turning the enable bit off and on. The four PWM channel outputs share general-purpose port P pins. Enabling PWM pins takes precedence over the general-purpose port. When PWM are not in use, the port pins may be used for discrete input/output.
CLOCK SOURCE (PCLK)
CENTR = 0 UP/DOWN FROM PORT P DATA REGISTER
GATE (CLOCK EDGE SYNC) RESET
PWCNTx
8-BIT COMPARE = PWDTYx S Q Q 8-BIT COMPARE = PWPERx R MUX MUX TO PIN DRIVER PPOLx
PWENx PPOL = 0
PPOL = 1 PWDTY PWPER
Figure 15 Block Diagram of PWM Left-Aligned Output Channel
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 63
CLOCK SOURCE (PCLK)
CENTR = 1 RESET FROM PORT P DATA REGISTER
GATE (CLOCK EDGE SYNC)
PWCNTx (DUTY CYCLE) UP/DOWN 8-BIT COMPARE = PWDTYx (PERIOD) 8-BIT COMPARE = PWPERx T Q Q
MUX
MUX TO PIN DRIVER
PPOLx PWENx PPOL = 0 PPOL = 1 PWDTY (PWPER - PWDTY) x 2 PWPER x 2 PWDTY
Figure 16 Block Diagram of PWM Center-Aligned Output Channel
MOTOROLA 64
MC68HC912B32 MC68HC912B32TS/D
PSBCK LIMBDM PCLK 0:0:0
PSBCK IS BIT 0 OF PWCTL REGISTER. INTERNAL SIGNAL LIMBDM IS ONE IF THE MCU IS IN BACKGROUND DEBUG MODE. CLOCK A 0:0:0 8-BIT DOWN COUNTER 0:0:1 0:1:0 =0 CLOCK S0* MUX PWSCNT0 PCLK0 CLOCK TO PWM CHANNEL 1 8-BIT SCALE REGISTER 0:1:1 PWSCAL0 CLOCK TO PWM CHANNEL 0
/2 /2 /2 /2 /2 /2 /2
REGISTER: PWPRES
0:0:1
0:1:0
0:1:1
/2
PCLK1
1:0:0
1:0:0 CLOCK B
MUX =0 CLOCK S1** PCLK2 MUX
1:0:1
1:0:1
CLOCK TO PWM CHANNEL 2
1:1:0
1:1:0
8-BIT DOWN COUNTER PWSCNT1
1:1:1 BITS: PCKB2, PCKB1, PCKB0
1:1:1 BITS: PCKA2, PCKA1, PCKA0
8-BIT SCALE REGISTER PWSCAL1
/2
PCLK3
*CLOCK S0 = (CLOCK A)/2, (CLOCK A)/4, (CLOCK A)/6,... (CLOCK A)/512 **CLOCK S1 = (CLOCK B)/2, (CLOCK B)/4, (CLOCK B)/6,... (CLOCK B)/512
Figure 17 PWM Clock Sources 11.1 PWM Register Description PWCLK -- PWM Clocks and Concatenate
Bit 7 CON23 RESET: 0 6 CON01 0 5 PCKA2 0 4 PCKA1 0 3 PCKA0 0 2 PCKB2 0 1 PCKB1 0 Bit 0 PCKB0 0
MUX
CLOCK TO PWM CHANNEL 3
$0040
Read and write anytime. CON23 -- Concatenate PWM Channels 2 and 3 When concatenated, channel 2 becomes the high-order byte and channel 3 becomes the low-order byte. Channel 2 output pin is used as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clockselect control bits determines the clock source. 0 = Channels 2 and 3 are separate 8-bit PWMs. 1 = Channels 2 and 3 are concatenated to create one 16-bit PWM channel.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 65
CON01 -- Concatenate PWM Channels 0 and 1 When concatenated, channel 0 becomes the high-order byte and channel 1 becomes the low-order byte. Channel 0 output pin is used as the output for this 16-bit PWM (bit 0 of port P). Channel 1 clockselect control bits determine the clock source. 0 = Channels 0 and 1 are separate 8-bit PWMs. 1 = Channels 0 and 1 are concatenated to create one 16-bit PWM channel. PCKA2 - PCKA0 -- Prescaler for Clock A Clock A is one of two clock sources which may be used for channels 0 and 1. These three bits determine the rate of clock A, as shown in Table 22. PCKB2 - PCKB0 -- Prescaler for Clock B Clock B is one of two clock sources which may be used for channels 2 and 3. These three bits determine the rate of clock B, as shown in Table 22. Table 22 Clock A and Clock B Prescaler
PCKA2 (PCKB2) 0 0 0 0 1 1 1 1 PCKA1 (PCKB1) 0 0 1 1 0 0 1 1 PCKA0 (PCKB0) 0 1 0 1 0 1 0 1 Value of Clock A (B) P P/2 P/4 P/8 P / 16 P / 32 P / 64 P / 128
PWPOL -- PWM Clock Select and Polarity
Bit 7 PCLK3 RESET: 0 6 PCLK2 0 5 PCLK1 0 4 PCLK0 0 3 PPOL3 0 2 PPOL2 0 1 PPOL1 0 Bit 0 PPOL0 0
$0041
Read and write anytime. PCLK3 -- PWM Channel 3 Clock Select 0 = Clock B is the clock source for channel 3. 1 = Clock S1 is the clock source for channel 3. PCLK2 -- PWM Channel 2 Clock Select 0 = Clock B is the clock source for channel 2. 1 = Clock S1 is the clock source for channel 2. PCLK1 -- PWM Channel 1 Clock Select 0 = Clock A is the clock source for channel 1. 1 = Clock S0 is the clock source for channel 1. PCLK0 -- PWM Channel 0 Clock Select 0 = Clock A is the clock source for channel 0. 1 = Clock S0 is the clock source for channel 0. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may occur during the transition.
MOTOROLA 66
MC68HC912B32 MC68HC912B32TS/D
PPOL3 -- PWM Channel 3 Polarity 0 = Channel 3 output is low at the beginning of the clock cycle; high when the duty count is reached. 1 = Channel 3 output is high at the beginning of the clock cycle; low when the duty count is reached. PPOL2 -- PWM Channel 2 Polarity 0 = Channel 2 output is low at the beginning of the clock cycle; high when the duty count is reached. 1 = Channel 2 output is high at the beginning of the clock cycle; low when the duty count is reached. PPOL1 -- PWM Channel 1 Polarity 0 = Channel 1 output is low at the beginning of the clock cycle; high when the duty count is reached. 1 = Channel 1 output is high at the beginning of the clock cycle; low when the duty count is reached. PPOL0 -- PWM Channel 0 Polarity 0 = Channel 0 output is low at the beginning of the clock cycle; high when the duty count is reached. 1 = Channel 0 output is high at the beginning of the clock cycle; low when the duty count is reached. Depending on the polarity bit, the duty registers may contain the count of either the high time or the low time. If the polarity bit is zero and left alignment is selected, the duty registers contain a count of the low time. If the polarity bit is one, the duty registers contain a count of the high time. For center-aligned operation the high or low time is multiplied by two. PWEN -- PWM Enable
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 PWEN3 0 2 PWEN2 0 1 PWEN1 0 Bit 0 PWEN0 0
$0042
Setting any of the PWENx bits causes the associated port P line to become an output regardless of the state of the associated data direction register (DDRP) bit. This does not change the state of the data direction bit. When PWENx returns to zero, the data direction bit controls I/O direction. On the front end of the PWM channel, the scaler clock is enabled to the PWM circuit by the PWENx enable bit being high. When all four PWM channels are disabled, the prescaler counter shuts off to save power. There is an edge-synchronizing gate circuit to guarantee that the clock will only be enabled or disabled at an edge. Read and write anytime. PWEN3 -- PWM Channel 3 Enable The pulse modulated signal will be available at port P, bit 3 when its clock source begins its next cycle. 0 = Channel 3 is disabled. 1 = Channel 3 is enabled. PWEN2 -- PWM Channel 2 Enable The pulse modulated signal will be available at port P, bit 2 when its clock source begins its next cycle. 0 = Channel 2 is disabled. 1 = Channel 2 is enabled. PWEN1 -- PWM Channel 1 Enable The pulse modulated signal will be available at port P, bit 1 when its clock source begins its next cycle. 0 = Channel 1 is disabled. 1 = Channel 1 is enabled. PWEN0 -- PWM Channel 0 Enable The pulse modulated signal will be available at port P, bit 0 when its clock source begins its next cycle. 0 = Channel 0 is disabled. 1 = Channel 0 is enabled.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 67
PWPRES -- PWM Prescale Counter
Bit 7 0 RESET: 0 6 Bit 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0043
PWPRES is a free-running 7-bit counter. Read anytime. Write only in special mode (SMOD = 1). PWSCAL0 -- PWM Scale Register 0
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0044
Read and write anytime. A write will cause the scaler counter PWSCNT0 to load the PWSCAL0 value unless in special mode with DISCAL = 1 in the PWTST register. PWM channels 0 and 1 can select clock S0 (scaled) as its input clock by setting the control bit PCLK0 and PCLK1 respectively. Clock S0 is generated by dividing clock A by the value in the PWSCAL0 register and dividing again by two. When PWSCAL0 = $00, clock A is divided by 256 then divided by two to generate clock S0. PWSCNT0 -- PWM Scale Counter 0 Value
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0045
PWSCNT0 is a down-counter that, upon reaching $00, loads the value of PWSCAL0. Read any time. PWSCAL1 -- PWM Scale Register 1
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0046
Read and write anytime. A write will cause the scaler counter PWSCNT1 to load the PWSCAL1 value unless in special mode with DISCAL = 1 in the PWTST register. PWM channels 2 and 3 can select clock S1 (scaled) as its input clock by setting the control bit PCLK2 and PCLK3 respectively. Clock S1 is generated by dividing clock B by the value in the PWSCAL1 register and dividing again by two. When PWSCAL1 = $00, clock B is divided by 256 then divided by two to generate clock S1. PWSCNT1 -- PWM Scale Counter 1 Value
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0047
PWSCNT1 is a down-counter that, upon reaching $00, loads the value of PWSCAL1. Read any time.
MOTOROLA 68
MC68HC912B32 MC68HC912B32TS/D
PWCNTx -- PWM Channel Counters
Bit 7 PWCNT0 PWCNT1 PWCNT2 PWCNT3 RESET: Bit 7 Bit 7 Bit 7 Bit 7 0 6 6 6 6 6 0 5 5 5 5 5 0 4 4 4 4 4 0 3 3 3 3 3 0 2 2 2 2 2 0 1 1 1 1 1 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 $0048 $0049 $004A $004B
Read and write anytime. A write will cause the PWM counter to reset to $00. In special mode, if DISCR = 1, a write does not reset the PWM counter. Each counter may be read any time without affecting the count or the operation of the corresponding PWM channel. Writes to a counter cause the counter to be reset to $00 and force an immediate load of both duty and period registers with new values. To avoid a truncated PWM period, write to a counter while the counter is disabled. In left-aligned output mode, resetting the counter and starting the waveform output is controlled by a match between the period register and the value in the counter. In centeraligned output mode the counters operate as up/down counters, where a match in period changes the counter direction. The duty register changes the state of the output during the period to determine the duty. When a channel is enabled, the associated PWM counter starts at the count in the PWCNTx register using the clock selected for that channel. In special mode, when DISCP = 1 and configured for left-aligned output, a match of period does not reset the associated PWM counter, and when configured center-aligned-output mode, a match of period does not change the associated PWM counter direction. PWPERx -- PWM Channel Period Registers
Bit 7 PWPER0 PWPER1 PWPER2 PWPER3 RESET: Bit 7 Bit 7 Bit 7 Bit 7 0 6 6 6 6 6 0 5 5 5 5 5 0 4 4 4 4 4 0 3 3 3 3 3 0 2 2 2 2 2 0 1 1 1 1 1 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 $004C $004D $004E $004F
Read and write anytime. The value in the period register determines the period of the associated PWM channel. If written while the channel is enabled, the new value will not take effect until the existing period terminates, forcing the counter to reset. The new period is then latched and is used until a new period value is written. Reading this register returns the most recent value written. To start a new period immediately, write the new period value and then write the counter forcing a new period to start with the new period value. Period = Channel-Clock-Period / (PWPER + 1) Period = Channel-Clock-Period / (2 x (PWPER + 1)) (CENTR = 0) (CENTR = 1)
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 69
PWDTYx -- PWM Channel Duty Registers
Bit 7 PWDTY0 PWDTY1 PWDTY2 PWDTY3 RESET: Bit 7 Bit 7 Bit 7 Bit 7 0 6 6 6 6 6 0 5 5 5 5 5 0 4 4 4 4 4 0 3 3 3 3 3 0 2 2 2 2 2 0 1 1 1 1 1 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 $0050 $0051 $0052 $0053
Read and write anytime. The value in each duty register determines the duty of the associated PWM channel. When the duty value is equal to the counter value, the output changes state. If the register is written while the channel is enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. Reading this register returns the most recent value written. If the duty register is greater than or equal to the value in the period register, there will be no duty change in state. If the duty register is set to $FF the output will always be in the state which would normally be the state opposite the PPOLx value. Left-Aligned-Output Mode (CENTR = 0): Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] x 100% Duty cycle = [(PWPERx - PWDTYx) / (PWPERx + 1)] x 100% Center-Aligned-Output Mode (CENTR = 1): Duty cycle = [(PWPERx - PWDTYx) / (PWPERx + 1)] x 100% Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] x 100% PWCTL -- PWM Control Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 PSWAI 0 3 CENTR 0 2 RDPP 0 1 PUPP 0 Bit 0 PSBCK 0
(PPOLx = 1) (PPOLx = 0) (PPOLx = 1) (PPOLx = 0) $0054
Read and write anytime. PSWAI -- PWM Halts while in Wait Mode 0 = Allows PWM main clock generator to continue while in wait mode. 1 = Halt PWM main clock generator when the part is in wait mode. CENTR -- Center-Aligned Output Mode To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are disabled. 0 = PWM channels operate in left-aligned output mode 1 = PWM channels operate in center-aligned output mode RDPP -- Reduced Drive of Port P 0 = All port P output pins have normal drive capability. 1 = All port P output pins have reduced drive capability. PUPP -- Pull-Up Port P Enable 0 = All port P pins have an active pull-up device disabled. 1 = All port P pins have an active pull-up device enabled.
MOTOROLA 70
MC68HC912B32 MC68HC912B32TS/D
PSBCK -- PWM Stops while in Background Mode 0 = Allows PWM to continue while in background mode. 1 = Disable PWM input clock when the part is in background mode. PWTST -- PWM Special Mode Register ("Test")
Bit 7 DISCR RESET: 0 6 DISCP 0 5 DISCAL 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$0055
Read anytime but write only in special mode (SMODN = 0). These bits are available only in special mode and are reset in normal mode. DISCR -- Disable Reset of Channel Counter on Write to Channel Counter 0 = Normal operation. Write to PWM channel counter will reset channel counter. 1 = Write to PWM channel counter does not reset channel counter. DISCP -- Disable Compare Count Period 0 = Normal operation 1 = In left-aligned output mode, match of period does not reset the associated PWM counter register. In center-aligned output mode, match of period does not change the associated PWM counter direction. DISCAL -- Disable Load of Scale-Counters on Write to the Associated Scale-Registers 0 = Normal operation 1 = Write to PWSCAL0 and PWSCAL1 does not load scale counters PORTP -- Port P Data Register
Bit 7 PP7 PWM RESET: - - 6 PP6 - - 5 PP5 - - 4 PP4 - - 3 PP3 PWM3 - 2 PP2 PWM2 - 1 PP1 PWM1 - Bit 0 PP0 PWM0 -
$0056
PWM functions share port P pins 3 to 0 and take precedence over the general-purpose port when enabled. PORTP can be read anytime. When configured as input, a read will return the pin level. When configured as output, a read will return the latched output data. A write will drive associated pins only if configured for output and the corresponding PWM channel is not enabled. After reset, all pins are general-purpose, high-impedance inputs. DDRP -- Port P Data Direction Register
Bit 7 DDP7 RESET: 0 6 DDP6 0 5 DDP5 0 4 DDP4 0 3 DDP3 0 2 DDP2 0 1 DDP1 0 Bit 0 DDP0 0
$0057
DDRP determines pin direction of port P when used for general-purpose I/O. When cleared, I/O pin is configured for input. When set, I/O pin is configured for output. Read and write anytime.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 71
11.2 PWM Boundary Cases The boundary conditions for the PWM channel duty registers and the PWM channel period registers cause these results: Table 23 PWM Boundary Conditions
PWDTYx $FF $FF PWPERx PWPERx - - PWPERx >$00 >$00 - - $00 $00 PPOLx 1 0 1 0 1 0 Output High Low High Low High Low
MOTOROLA 72
MC68HC912B32 MC68HC912B32TS/D
12 Standard Timer Module
The standard timer module consists of a 16-bit software-programmable counter driven by a prescaler. It contains eight complete 16-bit input capture/output compare channels and one 16-bit pulse accumulator. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from less than a microsecond to many seconds. It can also generate PWM signals without CPU intervention.
PRESCALER DIVIDE CTL TIMER COUNT REGISTER
CONTROL REGISTERS TCRE (COUNTER RESET) TCNT
TCTL1 & TCTL2 FUNCTION, DIRECTION, AND POLARITY CTL
MODULE CLOCK
PRESCALER PR2, PR1, PR0
16-BIT COUNTER
TCNT RESET OC7
IC INPUT INPUT CAPTURE/ OUTPUT COMPARE REGISTER BUFFER LATCH - TIOC INT TIMPT PIN LOGIC
PAD
INTERMODULE BUS
16-BIT COMPARATOR
TFF OC OUTPUT
CONTROL REGISTERS PAMOD GATE CLOCK CTL POLARITY CTL TC7 INPUT PIN
PULSE ACCUMULATOR 16-BIT COUNTER MUX TC7 PIN LOGIC
INT
PAD
BUFFER LATCH
/ 64
MODULE CLOCK
Figure 18 Timer Block Diagram: Input Capture, Output Compare, Pulse Accumulator
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 73
12.1 Timer Registers Input/output pins default to general-purpose I/O lines until an internal function which uses that pin is specifically enabled. The timer overrides the state of the DDR to force the I/O state of each associated port line when an output compare using a port line is enabled. In these cases the data direction bits will have no affect on these lines. When a pin is assigned to output an on-chip peripheral function, writing to this PORTTn bit does not affect the pin but the data is stored in an internal latch such that if the pin becomes available for generalpurpose output the driven level will be the last value written to the PORTTn bit. TIOS -- Timer Input Capture/Output Compare Select
Bit 7 IOS7 RESET: 0 6 IOS6 0 5 IOS5 0 4 IOS4 0 3 IOS3 0 2 IOS2 0 1 IOS1 0 Bit 0 IOS0 0
$0080
Read or write anytime. IOS[7:0] -- Input Capture or Output Compare Channel Configuration 0 = The corresponding channel acts as an input capture 1 = The corresponding channel acts as an output compare. CFORC -- Timer Compare Force Register
Bit 7 FOC7 RESET: 0 6 FOC6 0 5 FOC5 0 4 FOC4 0 3 FOC3 0 2 FOC2 0 1 FOC1 0 Bit 0 FOC0 0
$0081
Read anytime but will always return $00 (1 state is transient). Write anytime. FOC[7:0] -- Force Output Compare Action for Channel 7-0 A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare "n" to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set. OC7M -- Output Compare 7 Mask Register
Bit 7 OC7M7 RESET: 0 6 OC7M6 0 5 OC7M5 0 4 OC7M4 0 3 OC7M3 0 2 OC7M2 0 1 OC7M1 0 Bit 0 OC7M0 0
$0082
Read or write anytime. The bits of OC7M correspond bit-for-bit with the bits of timer port (PORTT). Setting the OC7Mn will set the corresponding port to be an output port regardless of the state of the DDRTn bit when the corresponding TIOSn bit is set to be an output compare. This does not change the state of the DDRT bits. OC7D -- Output Compare 7 Data Register
Bit 7 OC7D7 RESET: 0 6 OC7D6 0 5 OC7D5 0 4 OC7D4 0 3 OC7D3 0 2 OC7D2 0 1 OC7D1 0 Bit 0 OC7D0 0
$0083
Read or write anytime. The bits of OC7D correspond bit-for-bit with the bits of timer port (PORTT). When a successful OC7 compare occurs, for each bit that is set in OC7M, the corresponding data bit in OC7D is stored to the corresponding bit of the timer port.
MOTOROLA 74
MC68HC912B32 MC68HC912B32TS/D
When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit. TCNT -- Timer Count Register
Bit 7 Bit 15 Bit 7 RESET: 0 6 14 6 0 5 13 5 0 4 12 4 0 3 11 3 0 2 10 2 0 1 9 1 0
$0084-$0085
Bit 0 Bit 8 Bit 0 0
A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read anytime. Write has no meaning or effect in the normal mode; only writable in special modes (SMODN = 0). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. TSCR -- Timer System Control Register
Bit 7 TEN RESET: 0 6 TSWAI 0 5 TSBCK 0 4 TFFCA 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$0086
Read or write anytime. TEN -- Timer Enable 0 = Disables the timer, including the counter. Can be used for reducing power consumption. 1 = Allows the timer to function normally. If for any reason the timer is not active, there is no /64 clock for the pulse accumulator since the E/64 is generated by the timer prescaler. TSWAI -- Timer Stops While in Wait 0 = Allows the timer to continue running during wait. 1 = Disables the timer when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSBCK -- Timer Stops While in Background Mode 0 = Allows the timer to continue running while in background mode. 1 = Disables the timer whenever the MCU is in background mode. This is useful for emulation. TFFCA -- Timer Fast Flag Clear All 0 = Allows the timer flag clearing to function normally. 1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel ($90- $9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any access to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register ($A2, $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1). This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. TQCR -- Reserved
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$0087
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 75
TCTL1 -- Timer Control Register 1
Bit 7 OM7 RESET: 0 6 OL7 0 5 OM6 0 4 OL6 0 3 OM5 0 2 OL5 0 1 OM4 0 Bit 0 OL4 0
$0088
TCTL2 -- Timer Control Register 2
Bit 7 OM3 RESET: 0 6 OL3 0 5 OM2 0 4 OL2 0 3 OM1 0 2 OL1 0 1 OM0 0 Bit 0 OL0 0
$0089
Read or write anytime. OMn -- Output Mode OLn -- Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an output tied to OCn regardless of the state of the associated DDRT bit. Table 24 Compare Result Output Action
OMn 0 0 1 1 OLn 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one
TCTL3 -- Timer Control Register 3
Bit 7 EDG7B RESET: 0 6 EDG7A 0 5 EDG6B 0 4 EDG6A 0 3 EDG5B 0 2 EDG5A 0 1 EDG4B 0 Bit 0 EDG4A 0
$008A
TCTL4 -- Timer Control Register 4
Bit 7 EDG3B RESET: 0 6 EDG3A 0 5 EDG2B 0 4 EDG2A 0 3 EDG1B 0 2 EDG1A 0 1 EDG0B 0 Bit 0 EDG0A 0
$008B
Read or write anytime. EDGnB, EDGnA -- Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits. Table 25 Edge Detector Circuit Configuration
EDGnB 0 0 1 1 EDGnA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling)
MOTOROLA 76
MC68HC912B32 MC68HC912B32TS/D
TMSK1 -- Timer Interrupt Mask 1
Bit 7 C7I RESET: 0 6 C6I 0 5 C5I 0 4 C4I 0 3 C3I 0 2 C2I 0 1 C1I 0 Bit 0 C0I 0
$008C
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a hardware interrupt. Read or write anytime. C7I-C0I -- Input Capture/Output Compare "x" Interrupt Enable. TMSK2 -- Timer Interrupt Mask 2
Bit 7 TOI RESET: 0 6 0 0 5 PUPT 0 4 RDPT 0 3 TCRE 0 2 PR2 0 1 PR1 0 Bit 0 PR0 0
$008D
Read or write anytime. TOI -- Timer Overflow Interrupt Enable 0 = Interrupt inhibited 1 = Hardware interrupt requested when TOF flag set PUPT -- Timer Pull-Up Resistor Enable This enable bit controls pull-up resistors on the timer port pins when the pins are configured as inputs. 1 = Enable pull-up resistor function 0 = Disable pull-up resistor function RDPT -- Timer Drive Reduction This bit reduces the effective output driver size which can reduce power supply current and generated noise depending upon pin loading. 1 = Enable output drive reduction function 0 = Normal output drive capability TCRE -- Timer Counter Reset Enable This bit allows the timer counter to be reset by a successful output compare 7 event. 0 = Counter reset inhibited and counter free runs 1 = Counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never get set even though TCNT will count from $0000 through $FFFF. PR2, PR1, PR0 -- Timer Prescaler Select These three bits specify the number of /2 stages that are to be inserted between the module clock and the timer counter. Table 26 Prescaler Selection
PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 Reserved Reserved
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 77
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. TFLG1 -- Timer Interrupt Flag 1
Bit 7 C7F RESET: 0 6 C6F 0 5 C5F 0 4 C4F 0 3 C3F 0 2 C2F 0 1 C1F 0 Bit 0 C0F 0
$008E
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a one to the bit. Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel ($90-$9F) will cause the corresponding channel flag CnF to be cleared. C7F-C0F -- Input Capture/Output Compare Channel "n" Flag. TFLG2 -- Timer Interrupt Flag 2
Bit 7 TOF RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$008F
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit to one. Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. TOF -- Timer Overflow Flag Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.) TC0 -- Timer Input Capture/Output Compare Register 0
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$0090-$0091
Bit 0 Bit 8 Bit 0
TC1 -- Timer Input Capture/Output Compare Register 1
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$0092-$0093
Bit 0 Bit 8 Bit 0
TC2 -- Timer Input Capture/Output Compare Register 2
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$0094-$0095
Bit 0 Bit 8 Bit 0
MOTOROLA 78
MC68HC912B32 MC68HC912B32TS/D
TC3 -- Timer Input Capture/Output Compare Register 3
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$0096-$0097
Bit 0 Bit 8 Bit 0
TC4 -- Timer Input Capture/Output Compare Register 4
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$0098-$0099
Bit 0 Bit 8 Bit 0
TC5 -- Timer Input Capture/Output Compare Register 5
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$009A-$009B
Bit 0 Bit 8 Bit 0
TC6 -- Timer Input Capture/Output Compare Register 6
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$009C-$009D
Bit 0 Bit 8 Bit 0
TC7 -- Timer Input Capture/Output Compare Register 7
Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1
$009E-$009F
Bit 0 Bit 8 Bit 0
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read anytime. Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to $0000. PACTL -- Pulse Accumulator Control Register
Bit 7 0 RESET: 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 CLK1 0 2 CLK0 0 1 PAOVI 0 Bit 0 PAI 0
$00A0
Read or write anytime. PAEN -- Pulse Accumulator System Enable 0 = Pulse accumulator system disabled 1 = Pulse accumulator system enabled PAEN is independent from TEN. PAMOD -- Pulse Accumulator Mode 0 = Event counter mode 1 = Gated time accumulation mode
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 79
PEDGE -- Pulse Accumulator Edge Control For PAMOD = 0 (event counter mode) 0 = Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented 1 = Rising edges on the pulse accumulator input pin cause the count to be incremented For PAMOD = 1 (gated time accumulation mode) 0 = Pulse accumulator input pin high enables E / 64 clock to pulse accumulator and the trailing falling edge on the pulse accumulator input pin sets the PAIF flag. 1 = Pulse accumulator input pin low enables E / 64 clock to pulse accumulator and the trailing rising edge on the pulse accumulator input pin sets the PAIF flag. If the timer is not active (TEN = 0 in TSCR), there is no /64 clock since the E / 64 clock is generated by the timer prescaler. CLK1, CLK0 -- Clock Select Register Table 27 Clock Selection
CLK1 0 0 1 1 CLK0 0 1 0 1 Selected Clock Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. PAOVI -- Pulse Accumulator Overflow Interrupt Enable 0 = Interrupt inhibited 1 = Interrupt requested if PAOVF is set PAI -- Pulse Accumulator Input Interrupt Enable 0 = Interrupt inhibited 1 = Interrupt requested if PAIF is set PAFLG -- Pulse Accumulator Flag Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 PAOVF 0 Bit 0 PAIF 0
$00A1
Read or write anytime. When TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register. PAOVF -- Pulse Accumulator Overflow Flag Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit is cleared automatically by a write to the PAFLG register with bit 1 set. PAIF -- Pulse Accumulator Input Edge Flag Set when the selected edge is detected at the pulse accumulator input pin. In event mode, the event edge triggers PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the pulse accumulator input pin triggers PAIF. This bit is cleared automatically by a write to the PAFLG register with bit 0 set.
MOTOROLA 80
MC68HC912B32 MC68HC912B32TS/D
PACNT -- 16-Bit Pulse Accumulator Count Register
Bit 7 Bit 15 Bit 7 RESET: 0 6 14 6 0 5 13 5 0 4 12 4 0 3 11 3 0 2 10 2 0 1 9 1 0
$00A2-$00A3
Bit 0 Bit 8 Bit 0 0
Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read or write anytime. TIMTST -- Timer Test Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 TCBYP 0 Bit 0 PCBYP 0
$00AD
Read anytime. Write only in special mode (SMODN = 0) TCBYP -- Timer Divider Chain Bypass 0 = Normal operation 1 = The 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed. The clock drives both halves directly. PCBYP -- Pulse Accumulator Divider Chain Bypass 0 = Normal operation 1 = The 16-bit pulse accumulator counter is divided into two 8-bit halves and the prescaler is bypassed. The clock drives both halves directly. PORTT -- Timer Port Data Register
Bit 7 PT7 TIMER PA I/OC7 PAI 6 PT6 I/OC6 5 PT5 I/OC5 4 PT4 I/OC4 3 PT3 I/OC3 2 PT2 I/OC2 1 PT1 I/OC1 Bit 0 PT0 I/OC0
$00AE
PORTT can be read anytime. When configured as an input, a read will return the pin level. When configured as output, a read will return the latched output data. NOTE Writes do not change pin state when the pin is configured for timer output. The minimum pulse width for pulse accumulator input should always be greater than two module clocks due to input synchronizer circuitry. The minimum pulse width for the input capture should always be greater than the width of two module clocks due to input synchronizer circuitry.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 81
DDRT -- Data Direction Register for Timer Port
Bit 7 DDT7 RESET: 0 6 DDT6 0 5 DDT5 0 4 DDT4 0 3 DDT3 0 2 DDT2 0 1 DDT1 0 Bit 0 DDT0 0
$00AF
Read or write anytime. 0 = Configures the corresponding I/O pin for input only 1 = Configures the corresponding I/O pin for output The timer forces the I/O state to be an output for each timer port pin associated with an enabled output compare. In these cases the data direction bits will not be changed but have no affect on the direction of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. Input captures do not override the DDRT settings. 12.2 Timer Operation in Modes STOP: Timer is off since both PCLK and ECLK are stopped. BDM: Timer keeps running, unless TSBCK = 1 WAIT: Counters keep running, unless TSWAI = 1 NORMAL: Timer keeps running, unless TEN = 0 TEN = 0: All timer operations are stopped, registers may be accessed. Gated pulse accumulator /64 clock is also disabled. PAEN = 0: All pulse accumulator operations are stopped, registers may be accessed.
MOTOROLA 82
MC68HC912B32 MC68HC912B32TS/D
13 Serial Interface
The serial interface of the MC68HC912B32 consists of two independent serial I/O sub-systems: the serial communication interface (SCI) and the serial peripheral interface (SPI). Each serial pin shares function with the general-purpose port pins of port S. The SCI is an NRZ type system that is compatible with standard RS-232 systems. The SCI system has a single wire operation mode which allows the unused pin to be available as general-purpose I/O. The SPI subsystem, which is compatible with the M68HC11 SPI, includes new features such as SS output and bidirectional mode. 13.1 Block Diagram
SERIAL INTERFACE
SCI
RxD TxD I/O I/O MISO/SISO PORT S I/O DRIVERS
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7
HC12B32 SI BLOCK
I/O
SPI
MOSI/MOMI SCK CS/SS
Figure 19 Serial Interface Block Diagram 13.2 Serial Communication Interface (SCI) The serial communication interface on the MC68HC912B32 is an NRZ format (one start, eight or nine data, and one stop bit) asynchronous communication system with independent internal baud rate generation circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one of which may be designated as a parity bit, odd or even). If enabled, parity is generated in hardware for transmitted and received data. Receiver parity errors are flagged in hardware. The baud rate generator is based on a modulus counter, allowing flexibility in choosing baud rates. There is a receiver wake-up feature, an idle line detect feature, a loop-back mode, and various error detection features. Two port pins provide the external interface for the transmitted data (TXD) and the received data (RXD).
MC68HC912B32 MC68HC912B32TS/D
DDRS/IOCTLR
MOTOROLA 83
MCLK
BAUD RATE CLOCK MSB PARITY GENERATOR
SCI TRANSMITTER LSB 10-11 BIT SHIFT REG TxD BUFFER/SC0DRL PIN CONTROL / DDRS / PORT S TxD PS1
DIVIDER Rx Baud Rate SC0BD/SELECT Tx Baud Rate
SC0CR1/SCI CTL 1
TxMTR CONTROL
DATA BUS
SC0CR2/SCI CTL 2
SC0SR1/INT STATUS
RxD PS0
INT REQUEST LOGIC
TO INTERNAL LOGIC
PARITY DETECT
DATA RECOVERY
SCI RECEIVER MSB LSB 10-11 BIT SHIFT REG TxD BUFFER/SC0DRL
SC0CR1/SCI CTL 1
WAKE-UP LOGIC SC0SR1/INT STATUS
SC0CR2/SCI CTL 2 INT REQUEST LOGIC
HC12B32 SCI BLOCK
Figure 20 Serial Communications Interface Block Diagram 13.2.1 Data Format The serial data format requires the following conditions: * An idle-line in the high state before transmission or reception of a message. * A start bit (logic zero), transmitted or received, that indicates the start of each character. * Data that is transmitted or received least significant bit (LSB) first. * A stop bit (logic one), used to indicate the end of a frame. (A frame consists of a start bit, a character of eight or nine data bits and a stop bit.) * A BREAK is defined as the transmission or reception of a logic zero for one frame or more. * This SCI supports hardware parity for transmit and receive.
MOTOROLA 84
MC68HC912B32 MC68HC912B32TS/D
13.2.2 SCI Baud Rate Generation The basis of the SCI baud rate generator is a 13-bit modulus counter. This counter gives the generator the flexibility necessary to achieve a reasonable level of independence from the CPU operating frequency and still be able to produce standard baud rates with a minimal amount of error. The clock source for the generator comes from the P Clock. Table 28 Baud Rate Generation
Desired BR Divisor for BR Divisor for SCI Baud Rate P = 4.0 MHz P = 8.0 MHz 110 2273 4545 300 833 1667 600 417 833 1200 208 417 2400 104 208 4800 52 104 9600 26 52 14400 17 35 19200 13 26 38400 -- 13
13.2.3 Register Descriptions Control and data registers for the SCI subsystem are described below. The memory address indicated for each register is the default address that is in use after reset. The entire 512-byte register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. SC0BDH -- SCI Baud Rate Control Register
Bit 7 BTST RESET: 0 6 BSPL 0 5 BRLD 0 4 SBR12 0 3 SBR11 0 2 SBR10 0 1 SBR9 0 Bit 0 SBR8 0 High
$00C0
SC0BDL -- SCI Baud Rate Control Register
Bit 7 SBR7 RESET: 0 6 SBR6 0 5 SBR5 0 4 SBR4 0 3 SBR3 0 2 SBR2 1 1 SBR1 0 Bit 0 SBR0 0
$00C1
Low
SC0BDH and SC0BDL are considered together as a 16-bit baud rate control register. Read any time. Write SBR[12:0] anytime. Low order byte must be written for change to take effect. Write SBR[15:13] only in special modes. The value in SBR[12:0] determines the baud rate of the SCI. The desired baud rate is determined by the following formula: MCLK SCI Baud Rate = -------------------16 x BR which is equivalent to: MCLK BR = ---------------------------------------------------16 x SCI Baud Rate BR is the value written to bits SBR[12:0] to establish baud rate. NOTE The baud rate generator is disabled until the TE or RE bit in SC0CR2 register is set for the first time after reset, and/or the baud rate generator is disabled when SBR[12:0] = 0.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 85
BTST -- Baud Register Test Reserved for test function BSPL -- Baud Rate Counter Split Reserved for test function BRLD -- Baud Rate Reload Reserved for test function SC0CR1 -- SCI Control Register 1
Bit 7 LOOPS RESET: 0 6 WOMS 0 5 RSRC 0 4 M 0 3 WAKE 0 2 ILT 0 1 PE 0 Bit 0 PT 0
$00C2
Read or write anytime. LOOPS -- SCI LOOP Mode/Single Wire Mode Enable 0 = SCI transmit and receive sections operate normally. 1 = SCI receive section is disconnected from the RXD pin and the RXD pin is available as general purpose I/O. The receiver input is determined by the RSRC bit. The transmitter output is controlled by the associated DDRS bit. Both the transmitter and the receiver must be enabled to use the LOOP or the single wire mode. If the DDRS bit associated with the TXD pin is set during the LOOPS = 1, the TXD pin outputs the SCI waveform. If the DDRS bit associated with the TXD pin is clear during the LOOPS = 1, the TXD pin becomes high (IDLE line state) for RSRC = 0 and high impedance for RSRC = 1. Refer to Table 29. WOMS -- Wired-Or Mode for Serial Pins This bit controls the two pins (TXD and RXD) associated with the SCI section. 0 = Pins operate in a normal mode with both high and low drive capability. To affect the RXD bit, that bit would have to be configured as an output (via DDRS) which is the single wire case when using the SCI. WOMS bit still affects general-purpose output on TXD and RXD pins when SCI is not using these pins. 1 = Each pin operates in an open drain fashion if that pin is declared as an output. RSRC -- Receiver Source When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver. 0 = Receiver input is connected to the transmitter internally (not TXD pin) 1 = Receiver input is connected to the TXD pin Table 29 Loop Mode Functions
LOOPS RSRC 0 1 1 1 1 1 1 x 0 0 0 1 1 1 DDS1(3) x 0 1 1 0 1 1 WOMS x 0/1 1 1 x 0 1 Function of Port S Bit 1/3 Normal Operations LOOP mode without TXD output (TXD = High Impedance) LOOP mode with TXD output (CMOS) LOOP mode with TXD output (open-drain) Single wire mode without TXD output (the pin is used as receiver input only, TXD = High Impedance) Single wire mode with TXD output (the output is also fed back to receiver input, CMOS) Single wire mode for the receiving and transmitting (open-drain)
M -- Mode (select character format) 0 = One start, eight data, one stop bit 1 = One start, eight data, ninth data, one stop bit
MOTOROLA 86
MC68HC912B32 MC68HC912B32TS/D
WAKE -- Wakeup by Address Mark/Idle 0 = Wake up by IDLE line recognition 1 = Wake up by address mark (last data bit set) ILT -- Idle Line Type Determines which of two types of idle line detection will be used by the SCI receiver. 0 = Short idle line mode is enabled. 1 = Long idle line mode is detected. In the short mode, the SCI circuitry begins counting ones in the search for the idle line condition immediately after the start bit. This means that the stop bit and any bits that were ones before the stop bit could be counted in that string of ones, resulting in earlier recognition of an idle line. In the long mode, the SCI circuitry does not begin counting ones in the search for the idle line condition until a stop bit is received. Therefore, the last byte's stop bit and preceding "1" bits do not affect how quickly an idle line condition can be detected. PE -- Parity Enable 0 = Parity is disabled. 1 = Parity is enabled. PT -- Parity Type If parity is enabled, this bit determines even or odd parity for both the receiver and the transmitter. 0 = Even parity is selected. An even number of ones in the data character causes the parity bit to be zero and an odd number of ones causes the parity bit to be one. 1 = Odd parity is selected. An odd number of ones in the data character causes the parity bit to be zero and an even number of ones causes the parity bit to be one. SC0CR2 -- SCI Control Register 2
Bit 7 TIE RESET: 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0
$00C3
Read or write anytime. TIE -- Transmit Interrupt Enable 0 = TDRE interrupts disabled 1 = SCI interrupt will be requested whenever the TDRE status flag is set. TCIE -- Transmit Complete Interrupt Enable 0 = TC interrupts disabled 1 = SCI interrupt will be requested whenever the TC status flag is set. RIE -- Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled 1 = SCI interrupt will be requested whenever the RDRF status flag or the OR status flag is set. ILIE -- Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt will be requested whenever the IDLE status flag is set. TE -- Transmitter Enable 0 = Transmitter disabled 1 = SCI transmit logic is enabled and the TXD pin (port S bit 1) is dedicated to the transmitter. The TE bit can be used to queue an idle preamble. RE -- Receiver Enable 0 = Receiver disabled 1 = Enables the SCI receive circuitry
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 87
RWU -- Receiver Wake-Up Control 0 = Normal SCI Receiver 1 = Enables the wake-up function and inhibits further receiver interrupts. Normally hardware wakes the receiver by automatically clearing this bit. SBK -- Send Break 0 = Break generator off 1 = Generate a break code (at least 10 or 11 contiguous zeros) As long as SBK remains set the transmitter will send zeros. When SBK is changed to zero, the current frame of all zeros is finished before the TxD line goes to the idle state. If SBK is toggled on and off, the transmitter will send 10 (or 11) zeros and then revert to mark idle or sending data. SC0SR1 -- SCI Status Register 1
Bit 7 TDRE RESET: 1 6 TC 1 5 RDRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 Bit 0 PF 0
$00C4
The bits in these registers are set by various conditions in the SCI hardware and are automatically cleared by special acknowledge sequences. The receive related flag bits in SC0SR1 (RDRF, IDLE, OR, NF, FE, and PF) are all cleared by a read of the SC0SR1 register followed by a read of the transmit/ receive data register L. However, only those bits which were set when SC0SR1 was read will be cleared by the subsequent read of the transmit/receive data register L. The transmit related bits in SC0SR1 (TDRE and TC) are cleared by a read of the SC0SR1 register followed by a write to the transmit/receive data register L. Read anytime (used in auto clearing mechanism). Write has no meaning or effect. TDRE -- Transmit Data Register Empty Flag New data will not be transmitted unless SC0SR1 is read before writing to the transmit data register. Reset sets this bit. 0 = SC0DR busy 1 = Any byte in the transmit data register is transferred to the serial shift register so new data may now be written to the transmit data register. TC -- Transmit Complete Flag Flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear by reading SC0SR1 with TC set and then writing to SC0DR. 0 = Transmitter busy 1 = Transmitter is idle RDRF -- Receive Data Register Full Flag Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF is set if a received character is ready to be read from SC0DR. Clear the RDRF flag by reading SC0SR1 with RDRF set and then reading SC0DR. 0 = SC0DR empty 1 = SC0DR full IDLE -- Idle Line Detected Flag Receiver idle line is detected (the receipt of a minimum of 10/11 consecutive ones). This bit will not be set by the idle line condition when the RWU bit is set. Once cleared, IDLE will not be set again until after RDRF has been set (after the line has been active and becomes idle again). 0 = RxD line is idle 1 = RxD line is active OR -- Overrun Error Flag New byte is ready to be transferred from the receive shift register to the receive data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared. 0 = No overrun 1 = Overrun detected
MOTOROLA 88
MC68HC912B32 MC68HC912B32TS/D
NF -- Noise Error Flag Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR). 0 = Unanimous decision 1 = Noise on a valid start bit, any of the data bits, or on the stop bit FE -- Framing Error Flag Set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SC0SR1 with FE set and then reading SC0DR. 0 = Stop bit detected 1 = Zero detected rather than a stop bit PF -- Parity Error Flag Indicates if received data's parity matches parity bit. This feature is active only when parity is enabled. The type of parity tested for is determined by the PT (parity type) bit in SC0CR1. 0 = Parity correct 1 = Incorrect parity detected SC0SR2 -- SCI Status Register 2
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 RAF 0
$00C5
Read anytime. Write has no meaning or effect. RAF -- Receiver Active Flag This bit is controlled by the receiver front end. It is set during the RT1 time period of the start bit search. It is cleared when an idle state is detected or when the receiver circuitry detects a false start bit (generally due to noise or baud rate mismatch). 0 = A character is not being received 1 = A character is being received SC0DRH -- SCI Data Register High
Bit 7 R8 RESET: 0 6 T8 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$00C6
SC0DRL -- SCI Data Register Low
Bit 7 R7/T7 RESET: 0 6 R6/T6 0 5 R5/T5 0 4 R4/T4 0 3 R3/T3 0 2 R2/T2 0 1 R1/T1 0 Bit 0 R0/T0 0
$00C7
R8 -- Receive Bit 8 Read anytime. Write has no meaning or affect. This bit is the ninth serial data bit received when the SCI system is configured for nine-data-bit operation. T8 -- Transmit Bit 8 Read or write anytime. This bit is the ninth serial data bit transmitted when the SCI system is configured for nine-data-bit operation. When using 9-bit data format this bit does not have to be written for each data word. The same value will be transmitted as the ninth bit until this bit is rewritten.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 89
R7/T7-R0/T0 -- Receive/Transmit Data Bits 7 to 0 Reads access the eight bits of the read-only SCI receive data register (RDR). Writes access the eight bits of the write-only SCI transmit data register (TDR). SC0DRL:SC0DRH form the 9-bit data word for the SCI. If the SCI is being used with a 7- or 8-bit data word, only SC0DRL needs to be accessed. If a 9-bit format is used, the upper register should be written first to ensure that it is transferred to the transmitter shift register with the lower register. 13.3 Serial Peripheral Interface (SPI) The serial peripheral interface allows the MC68HC912B32 to communicate synchronously with peripheral devices and other microprocessors. The SPI system in the MC68HC912B32 can operate as a master or as a slave. The SPI is also capable of interprocessor communications in a multiple master system. When the SPI is enabled, all pins that are defined by the configuration as inputs will be inputs regardless of the state of the DDRS bits for those pins. All pins that are defined as SPI outputs will be outputs only if the DDRS bits for those pins are set. Any SPI output whose corresponding DDRS bit is cleared can be used as a general-purpose input. A bidirectional serial pin is possible using the DDRS as the direction control. 13.3.1 SPI Baud Rate Generation The P clock is input to a divider series and the resulting SPI clock rate may be selected to be P divided by 2, 4, 8, 16, 32, 64, 128 or 256. Three bits in the SP0BR register control the SPI clock rate. This baud rate generator is activated only when SPI is in the master mode and serial transfer is taking place. Otherwise this divider is disabled to save power. 13.3.2 SPI Operation In the SPI system the 8-bit data register in the master and the 8-bit data register in the slave are linked to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the SCK clock from the master so the data is effectively exchanged between the master and the slave. Data written to the SP0DR register of the master becomes the output data for the slave and data read from the SP0DR register of the master after a transfer operation is the input data from the slave.
MOTOROLA 90
MC68HC912B32 MC68HC912B32TS/D
MCU P CLOCK (SAME AS E RATE) S M DIVIDER M S MISO PS4 MOSI PS5
/2 /4 /8 /16 /32 /64 /128 /256
8-BIT SHIFT REGISTER READ DATA BUFFER SP0DR SPI DATA REGISTER
SELECT SHIFT CONTROL LOGIC LSBF PIN CONTROL LOGIC CLOCK CLOCK LOGIC MSTR SPE SWOM WCOL MODF S M SCK PS6 SS PS7
SPR2
SP0BR SPI BAUD RATE REGISTER
SPI CONTROL
SPIF
SPR1
SPR0
SWOM
MSTR
CPHA
SSOE
CPOL
PUPS
SPI INTERRUPT REQUEST
SP0SR SPI STATUS REGISTER
SP0CR1 SPI CONTROL REGISTER 1
SP0CR2 SPI CONTROL REGISTER 2
INTERNAL BUS
HC12 SPI BLOCK
Figure 21 Serial Peripheral Interface Block Diagram A clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SP0CR1 register select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by shifting the clock by one half cycle or no phase shift.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 91
SPC0
LSBF
SPIE
RDS
SPE
Transfer SCK (CPOL=0) SCK (CPOL=1)
Begin
End
SAMPLE I (MOSI/MISO) CHANGE O (MOSI pin) CHANGE O (MISO pin) SEL SS (O) (Master only) SEL SS (I)
tL MSB first (LSBF=0) : LSB first (LSBF=1) : MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB tI tT tL Minimum 1/2 SCK for tT, tl, tL
HC12 SPI CLOCK FORM 0
Figure 22 SPI Clock Format 0 (CPHA = 0)
Transfer SCK (CPOL=0) SCK (CPOL=1)
Begin
End
SAMPLE I (MOSI/MISO) CHANGE O (MOSI pin) CHANGE O (MISO pin) SEL SS (O) (Master only) SEL SS (I)
tL MSB first (LSBF=0) : LSB first (LSBF=1) : tT MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB tI tL Minimum 1/2 SCK for tT, tl, tL
HC12 SPI CLOCK FORM 1
Figure 23 SPI Clock Format 1 (CPHA = 1)
MOTOROLA 92
MC68HC912B32 MC68HC912B32TS/D
13.3.3 SS Output Available in master mode only, SS output is enabled with the SSOE bit in the SP0CR1 register if the corresponding DDRS bit is set. The SS output pin will be connected to the SS input pin of the external slave device. The SS output automatically goes low for each transmission to select the external device and it goes high during each idling state to deselect external devices. Table 30 SS Output Selection
DDS7 0 0 1 1 SSOE 0 1 0 1 Master Mode SS Input with MODF Feature Reserved General-Purpose Output SS Output Slave Mode SS Input SS Input SS Input SS Input
13.3.4 Bidirectional Mode (MOMI or SISO) In bidirectional mode, the SPI uses only one serial data pin for external device interface. The MSTR bit decides which pin to be used. The MOSI pin becomes serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The direction of each serial I/O pin depends on the corresponding DDRS bit.
Master Mode MSTR=1 MO
DDS5
When SPE=1
Slave Mode MSTR=0 SI
DDS4
Normal Mode SPC0=0
Serial Out
Serial In
SPI
Serial In
SPI MI
Serial Out
SO
SWOM enables open drain output.
SWOM enables open drain output.
Bidirectional Mode SPC0=1
Serial Out
MOMI
DDS5
Serial In
PS5
DDS4
SPI
Serial In
SPI PS4
Serial Out
SISO
SWOM enables open drain output. PS4 becomes GPIO.
SWOM enables open drain output. PS5 becomes GPIO.
Figure 24 Normal Mode and Bidirectional Mode 13.3.5 Register Descriptions Control and data registers for the SPI subsystem are described below. The memory address indicated for each register is the default address that is in use after reset. The entire 512-byte register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. For more information refer to 5 Operating Modes and Resource Mapping. SP0CR1 -- SPI Control Register 1
Bit 7 SPIE RESET: 0 6 SPE 0 5 SWOM 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SSOE 0 Bit 0 LSBF 0
$00D0
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 93
Read or write anytime. SPIE -- SPI Interrupt Enable 1 = Hardware interrupt sequence is requested each time the SPIF or MODF status flag is set 0 = SPI interrupts are inhibited SPE -- SPI System Enable 0 = SPI internal hardware is initialized and SPI system is in a low-power disabled state. 1 = PS[4:7] are dedicated to the SPI function When MODF is set, SPE always reads zero. SP0CR1 must be written as part of a mode fault recovery sequence. SWOM -- Port S Wired-OR Mode Controls not only SPI output pins but also the general-purpose output pins (PS[4:7]) which are not used by SPI. 0 = SPI and/or PS[4:7] output buffers operate normally 1 = SPI and/or PS[4:7] output buffers behave as open-drain outputs MSTR -- SPI Master/Slave Mode Select 0 = Slave mode 1 = Master mode CPOL, CPHA -- SPI Clock Polarity, Clock Phase These two bits are used to specify the clock format to be used in SPI operations. When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device is low. When CPOL is set, SCK idles high. See Figure 22 and Figure 23. SSOE -- Slave Select Output Enable The SS output feature is enabled only in the master mode by asserting the SSOE and DDS7. LSBF -- SPI LSB First Enable 0 = Data is transferred most significant bit first 1 = Data is transferred least significant bit first Normally data is transferred most significant bit first. This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register will always have MSB in bit 7. SP0CR2 -- SPI Control Register 2
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 SSWAI 0 Bit 0 SPC0 0
$00D1
Read or write anytime. SSWAI -- SSI Stop in Wait Mode 0 = SSI clock operate normally 1 = Halt SSI clock generation when in wait mode SPC0 -- Serial Pin Control 0 This bit decides serial pin configurations with MSTR control bit.
MOTOROLA 94
MC68HC912B32 MC68HC912B32TS/D
Pin Mode #1 #2 #3 #4 Normal Bidirectional
SPC01 0 1
MSTR 0 1 0 1
MISO2 Slave Out Master In Slave I/O GPI/O
MOSI3 Slave In Master Out GPI/O Master I/O
SCK4 SCK In SCK Out SCK In SCK Out
SS5 SS In SS I/O SS In SS I/O
NOTES: 1. The serial pin control 0 bit enables bidirectional configurations. 2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3) 3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4) 4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4) 5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
SP0BR -- SPI Baud Rate Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 SPR2 0 1 SPR1 0 Bit 0 SPR0 0
$00D2
Read anytime. Write anytime. At reset, E Clock divided by 2 is selected. SPR[2:0] -- SPI Clock (SCK) Rate Select Bits These bits are used to specify the SPI clock rate. Table 31 SPI Clock Rate Selection
SPR2 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 E Clock Divisor 2 4 8 16 32 64 128 256 Frequency at Frequency at E Clock = 4 MHz E Clock = 8 MHz 2.0 MHz 1.0 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz 15.6 kHz 4.0 MHz 2.0 MHz 1.0 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz
SP0SR -- SPI Status Register
Bit 7 SPIF RESET: 0 6 WCOL 0 5 0 0 4 MODF 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$00D3
Read anytime. Write has no meaning or effect. SPIF -- SPI Interrupt Request SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SP0SR register (with SPIF set) followed by an access (read or write) to the SPI data register. WCOL -- Write Collision Status Flag The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 95
(read or write) to the SP0DR register. 0 = No write collision 1 = Indicates that a serial transfer was in progress when the MCU tried to write new data into the SP0DR data register. MODF -- SPI Mode Error Interrupt Status Flag This bit is set automatically by SPI hardware if the MSTR control bit is set and the slave select input pin becomes zero. This condition is not permitted in normal operation. In the case where DDRS bit 7 is set, the PS7 pin is a general-purpose output pin or SS output pin rather than being dedicated as the SS input for the SPI system. In this special case the mode fault function is inhibited and MODF remains cleared. This flag is automatically cleared by a read of the SP0SR (with MODF set) followed by a write to the SP0CR1 register. SP0DR -- SPI Data Register
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$00D5
Read anytime (normally only after SPIF flag set). Write anytime (see WCOL write collision flag). Reset does not affect this address. This 8-bit register is both the input and output register for SPI data. Reads of this register are double buffered but writes cause data to be written directly into the serial shifter. In the SPI system the 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO wires to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the SCK clock from the master so the data is effectively exchanged between the master and the slave. Note that some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. 13.4 Port S In all modes, port S bits PS[7:0] can be used for either general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as high-impedance inputs (DDRS is cleared). PORTS -- Port S Data Register
Bit 7 PS7 Pin Function SS CS 6 PS6 SCK 5 PS5 MOSI MOMI 4 PS4 MISO SISO 3 PS3 I/O 2 PS2 I/O 1 PS1 TXD0 Bit 0 PS0 RXD0
$00D6
PORTS can be read anytime. When configured as an input, a read will return the pin level. When configured as output, a read will return the latched output data. Writes do not change pin state when pin configured for SPI or SCI output. After reset all bits are configured as general-purpose inputs. Port S shares function with the on-chip serial systems (SPI0 and SCI0). DDRS -- Data Direction Register for Port S
Bit 7 DDS7 RESET: 0 6 DDS6 0 5 DDS5 0 4 DDS4 0 3 DDS3 0 2 DDS2 0 1 DDS1 0 Bit 0 DDS0 0
$00D7
Read or write anytime. After reset, all general-purpose I/O are configured for input only. 0 = Configure the corresponding I/O pin for input only 1 = Configure the corresponding I/O pin for output
MOTOROLA 96
MC68HC912B32 MC68HC912B32TS/D
DDS0 -- Data Direction for Port S Bit 2 and Bit 0 If the SCI receiver is configured for two-wire SCI operation, corresponding port S pins will be input regardless of the state of these bits. DDS1 -- Data Direction for Port S Bit 1 If the SCI transmitter is configured for two-wire SCI operation, corresponding port S pins will be output regardless of the state of these bits. DDS2, DDRS3 -- Data Direction for Port S Bit 2 and Bit 3 These bits are for general-purpose I/O only. DDS[6:4] -- Data Direction for Port S Bits 6 through 4 If the SPI is enabled and expects the corresponding port S pin to be an input, it will be an input regardless of the state of the DDRS bit. If the SPI is enabled and expects the bit to be an output, it will be an output only if the DDRS bit is set. DDS7 -- Data Direction for Port S Bit 7 In SPI slave mode, DDS7 has no meaning or effect; the PS7 pin is dedicated as the SS input. In SPI master mode, DDS7 determines whether PS7 is an error detect input to the SPI or a general-purpose or slave select output line. PURDS -- Pull-Up and Reduced Drive for Port S
Bit 7 0 RESET: 0 6 RDPS2 0 5 RDPS1 0 4 RDPS0 0 3 0 0 2 PUPS2 1 1 PUPS1 1 Bit 0 PUPS0 1
$00DB
Read or write anytime. RDPS2 -- Reduce Drive of PS[7:4] 0 = Port S output drivers for bits 7 through 4 operate normally. 1 = Port S output pins for bits 7 through 4 have reduced drive capability for lower power and less noise. RDPS1 -- Reduce Drive of PS[3:2] 0 = Port S output drivers for bits 3 and 2 operate normally. 1 = Port S output pins for bits 3 and 2 have reduced drive capability for lower power and less noise. RDPS0 -- Reduce Drive of PS[1:0] 0 = Port S output drivers for bits 1 and 0 operate normally. 1 = Port S output pins for bits 1 and 0 have reduced drive capability for lower power and less noise. PUPS2 -- Pull-Up Port S Enable PS[7:4] 0 = No internal pull-ups on port S bits 7 through 4. 1 = Port S input pins for bits 7 through 4 have an active pull-up device. If a pin is programmed as output, the pull-up device becomes inactive. PUPS1 -- Pull-Up Port S Enable PS[3:2] 0 = No internal pull-ups on port S bits 3 and 2. 1 = Port S input pins for bits 3 and 2 have an active pull-up device. If a pin is programmed as output, the pull-up device becomes inactive. PUPS0 -- Pull-Up Port S Enable PS[1:0] 0 = No internal pull-ups on port S bits 1 and 0. 1 = Port S input pins for bits 1 and 0 have an active pull-up device. If a pin is programmed as output, the pull-up device becomes inactive.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 97
14 Byte Data Link Communications Module (BDLC)
The byte data link communications module (BDLC) provides access to an external serial communication multiplex bus, operating according to the SAE J1850 protocol. 14.1 Features Features of the BDLC module include the following: * SAE J1850 compatible * 10.4 Kbps VPW bit format * Digital noise filter * Collision detection * Hardware CRC generation and checking * Two power saving modes with automatic wake up on network activity * Polling and CPU interrupts with vector lookup available * Receive and transmit block mode supported * Supports 4X receive mode (41.6 Kbps) * Digital loopback mode * In-frame response (IFR) types 0, 1, 2, and 3 supported * Dedicated register for symbol timing adjustments * Digital module only, requires external analog transceiver NOTE It is recommended that the reader be familiar with the SAE Standard J1850 Class B Data Communication Network Interface specification prior to proceeding with this section. 14.2 BDLC Operating Modes The BDLC has five main modes of operation which interact with the power supplies, pins and the MCU. Power Off is entered from the reset mode whenever the BDLC supply voltage VDD drops below the minimum value for guaranteed operation. In this mode, the pin input and output specifications are not guaranteed. Reset is entered from the power off mode whenever the BDLC supply voltage VDD rises above its minimum specified value and an MCU reset source is asserted. To prevent the BDLC from entering an unknown state, the internal MCU reset is asserted while powering up the BDLC. In reset mode, the internal BDLC voltage references are operative, VDD is supplied to the internal circuits, which are held in their reset state and the internal BDLC system clock is running. Registers will assume their reset condition. Outputs are held in their programmed reset state. Inputs and network activity are ignored. Run is entered from the reset mode after all MCU reset sources are no longer asserted. It is entered from the BDLC wait mode whenever activity is sensed on the J1850 bus. Run mode is entered from the BDLC stop mode whenever network activity is sensed though messages will not be received properly until the clocks have stabilized and the CPU is also in the run mode. In run mode, normal network operation takes place. Ensure that all BDLC transmissions cease before exiting this mode. BDLC Wait power-conserving mode is automatically entered from the run mode whenever the CPU executes a WAIT instruction and if the WCM bit in the BCR register has been cleared. In this mode, the BDLC internal clocks continue to run. The first passive-to-active transition of the bus wakes up the BDLC and the CPU. If a valid byte is successfully received a CPU interrupt request will be generated. BDLC Stop power-conserving mode is automatically entered from the run mode whenever the CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM bit in the BCR register has been set. In this mode, the BDLC internal clocks are stopped until network activity is sensed and a CPU interrupt request is generated.
MOTOROLA 98
MC68HC912B32 MC68HC912B32TS/D
14.3 Loopback Modes Two loopback modes are used to determine the source of bus faults. Digital Loopback is used to determine if a bus fault has been caused by failure in the node's internal circuits or elsewhere in the network, including the node's analog physical interface. In this mode, the receive digital input (RxPD) is disconnected from the analog transceiver's receive output. RxPD is then connected internally to the transmit digital output (TxPD) to form the loopback connection. The analog transceiver's transmit input is still driven by TxPD in this mode. Analog Loopback is used to determine if a bus fault has been caused by a failure in the node's off-chip analog transceiver or elsewhere in the network. The BDLC analog loopback mode does not modify the digital transmit or receive functions of the BDLC. It does, however, ensure that once analog loopback mode is exited, the BDLC will wait for an idle bus condition before participation in network communication resumes. If the off-chip analog transceiver has a loopback mode, it usually causes the input to the output drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted without driving the J1850 bus. In this mode, the output to the J1850 bus is typically high impedance. This allows the communication path through the analog transceiver to be tested without interfering with network activity. Using the BDLC analog loopback mode in conjunction with the analog transceiver's loopback mode ensures that, once the off-chip analog transceiver has exited loopback mode, the BDLC will not begin communicating before a known condition exists on the J1850 bus. 14.4 BDLC Registers Eight registers are available for controlling operation of the BDLC and for communicating data and status information. A full description of each register follows. BCR1 -- BDLC Control Register 1
Bit 7 IMSG RESET: 1 6 CLCKS 1 5 R1 1 4 R0 0 3 0 0 2 0 0 1 IE 0 Bit 0 WCM 0
$00F8
IMSG -- Ignore Message Disables the receiver until a new start-of-frame (SOF) is detected. 0 = Enable Receiver 1 = Disable Receiver CLKS -- Clock Select Designates nominal BDLC operating frequency (fbdlc) for J1850 bus communication and automatic adjustment of symbol time. 0 = Integer frequency (1 MHz) 1 = Binary frequency (1.048576 MHz) R1, R0 -- Rate Select Determines the divisor of the MCU system clock frequency (fTCLKS) to form the BLDC operating frequency (fBDLC). These bits may be written only once after reset. The selected value depends upon the MCU system clock frequency according to Table 32 or Table 33.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 99
Table 32 BDLC Rate Selection for Binary Frequencies (fBDLC = 1.048576 MHz)
MCU Clock Frequency (fTCLKS) 1.048576 MHz 2.09715 MHz 4.19430 MHz 8.38861 MHz R1 0 0 1 1 R0 0 1 0 1 Division 1 2 4 8
Table 33 BDLC Rate Selection for Integer Frequencies (fBDLC = 1.000000 MHz)
MCU Clock Frequency (fTCLKS) 1.00000 MHz 2.00000 MHz 4.00000 MHz 8.00000 MHz R1 0 0 1 1 R0 0 1 0 1 Division 1 2 4 8
IE -- Interrupt Enable Determines whether the BDLC will generate CPU interrupt requests in the run mode. It does not affect CPU interrupt requests when exiting the BDLC stop or BDLC wait modes. 0 = Disable interrupt requests from BDLC 1 = Enable interrupt requests from BDLC WCM -- Wait Clock Mode Determines the operation of the BDLC during CPU wait mode 0 = Run BDLC internal clocks during CPU wait mode 1 = Stop BDLC internal clocks during CPU wait mode BCR2 -- BDLC Control Register 2
Bit 7 ALOOP RESET: 1 6 DLOOP 1 5 RX4XE 0 4 NBFS 0 3 TEOD 0 2 TSIFR 0 1 TMIFR1 0 Bit 0 TMIFR0 0
$00FA
Controls transmitter operations of the BDLC. ALOOP -- Analog Loopback Status Sets the BDLC state machine to a known state after the off-chip analog transceiver has been put in loop back mode. 0 = Off-chip analog transceiver has been taken out of analog loopback mode 1 = Off-chip analog transceiver has been put into analog loopback mode DLOOP -- Digital Loopback Mode Determines the RxPD source and can isolate bus fault conditions. If a fault condition is detected on the bus, RxPD can be disconnected from the analog transceiver's receive output and connected to TxPD to determine if the fault is in the digital block or elsewhere on the J1850 bus. 0 = RxPD is connected to the analog transceiver's receive output. The BDLC is taken out of digital loopback mode and can now drive and receive from the J1850 bus normally if ALOOP is not set. 1 = RxPD is connected to TxPD. The BDLC is now in digital loopback mode of operation. The analog transceiver's transmit input is still driven by TxPD.
MOTOROLA 100
MC68HC912B32 MC68HC912B32TS/D
RX4XE -- Receive 4X Enable Reception of a BREAK symbol automatically clears this bit and sets the BSVR register to $1C. 0 = BDLC transmits and receives at 10.4 kbps 1 = BDLC is in 4X receive only operation NBFS -- Normalization Bit Format Select Controls the format of the normalization bit. 0 = Normalization bit is a zero (0) when the response part of an in-frame response (IFR) does not end with a CRC byte. Normalization bit is a one (1) when the response part of an in-frame response (IFR) ends with a CRC byte. 1 = Normalization bit is a one (1) when the response part of an in-frame response (IFR) does not end with a CRC byte. Normalization bit is a zero (0) when the response part of an in-frame response (IFR) ends with a CRC byte. TEOD -- Transmit End of Data Marks the end of a BDLC message by appending an 8-bit CRC after completing transmission of the current byte. This bit is also used to end an IFR transmission. 0 = TEOD is automatically cleared at the rising edge of the first CRC bit or if an error is detected. When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC receives back a valid EOD symbol or an error condition occurs. 1 = Transmit EOD symbol TSIFR, TMIFR1, TMIFR0 -- Transmit In-Frame Response Control Controls the type of in-frame response being sent. If more than one bit is set, the bits will be interpreted according to Table 34 although the bits can be read back as they were set. Table 34 Transmit In-Frame Response Control Bit Priority Encoding
Write/Read TSIFR 0 1 0 0 1 0 1 TMIFR1 0 TMIFR0 0 TSIFR 0 1 0 0 Internal Interpretation TMIFR1 0 0 1 0 TMIFR0 0 0 0 1
Shaded cells indicate bits which do not affect internal interpretation. These bits will be read back as written.
The BDLC supports the in-frame response (IFR) features of J1850. The four types of J1850 IFR are shown below.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 101
TYPE 0 -- NO IFR EOF EOD SOF SOF SOF SOF HEADER DATA FIELD CRC
TYPE 1 -- SINGLE BYTE FROM A SINGLE RESPONDER EOF EOD EOD HEADER DATA FIELD CRC NB ID
TYPE 2 -- SINGLE BYTE FROM MULTIPLE RESPONDERS EOD EOF EOD HEADER DATA FIELD CRC NB ID1 IDn
TYPE 3 -- MULTIPLE BYTES FROM A SINGLE RESPONDER EOD EOF EOD HEADER DATA FIELD CRC NB IFR DATA FIELD CRC
Figure 25 Types of In-Frame Response TSIFR -- Transmit Single Byte IFR with No CRC (Type 1 and Type 2) Used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a single byte IFR with no CRC. 0 = TSIFR will be cleared automatically once the BDLC has successfully transmitted the byte in the BDR onto the bus, or TEOD is set by the CPU, or an error is detected on the bus. 1 = If set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by the byte in the BDR. TMIFR0 -- Transmit Multiple Byte IFR without CRC (Type 3) Used to request the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR without CRC. 0 = TMIFR0 will be cleared automatically once the BDLC has successfully transmitted the EOD symbol, by the detection of an error on the multiplex bus, or by a transmitter underrun caused when the programmer does not write another byte to the BDR following the TDRE interrupt. 1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into BDR register. After TEOD has been set, the last IFR byte to be transmitted will be the last byte which was written into the BDR register. TMIFR1 -- Transmit Multiple Byte IFR with CRC (Type 3) This bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR with CRC or as a single byte IFR with CRC. 0 = TMIFR1 will be cleared automatically once the BDLC has successfully transmitted the CRC byte and EOD symbol, by the detection of an error on the multiplex bus, or by a transmitter underrun caused when another byte is not written to the BDR following the TDRE interrupt. 1 = If set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. After TEOD has been set by software and the last IFR byte has been transmitted, the CRC byte is transmitted.
MOTOROLA 102
MC68HC912B32 MC68HC912B32TS/D
BSVR -- BDLC State Vector Register
Bit 7 0 RESET: 0 6 0 0 5 I3 0 4 I2 0 3 I1 0 2 I0 0 1 0 0 Bit 0 0 0
$00F9
Decreases the CPU overhead associated with servicing interrupts while operating a serial communication protocol. It provides an index offset that is directly related to the BDLC's current state. I0, I1, I2, I3 -- Interrupt Source Source of the pending interrupt request. Bits are encoded according to Table 35. Table 35 Interrupt Sources
BSVR $00 $04 $08 $0C $10 $14 $18 $1C $20 I3 0 0 0 0 0 0 0 0 1 I2 0 0 0 0 1 1 1 1 0 I1 0 0 1 1 0 0 1 1 0 I0 0 1 0 1 0 1 0 1 0 Interrupt Source No Interrupts Pending Received EOF Received IFR byte (RXIFR) Rx data register full (RDRF) Tx data register empty (TDRE) Loss of arbitration CRC error Symbol invalid or out of range Wakeup Priority 0 (lowest) 1 2 3 4 5 6 7 8 (highest)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR register except when the BDLC data register needs servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can only be cleared by a read of the BSVR register followed by a read of BDR. TDRE can either be cleared by a read of the BSVR register followed by a write to the BDLC BDR register, or by setting the TEOD bit in BCR2. Upon receiving a BDLC interrupt, the user may read the value within the BSVR, transferring it to the CPU's index register. The value can be used to index a jump table to access a service routine. For example: SERVICE * * JMPTAB LDX JMP BSVR JMPTAB,X Fetch State Vector Number Enter service routine, (must end in an RTI) Service condition #0 Service condition #1 Service condition #2
JMP NOP JMP NOP JMP NOP . . . JMP END
SERVE0 SERVE1 SERVE2
SERVE8
Service condition #8
NOP instructions are used to align the JMP instructions onto 4-byte boundaries so that the value in the BSVR may be used intact. Each of the service routines must end with an RTI instruction.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 103
BDR -- BDLC Data Register
Bit 7 D7 RESET: - 6 D6 - 5 D5 - 4 D4 - 3 D3 - 2 D2 - 1 D1 - Bit 0 D0 -
$00FB
Used to pass data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to pass data to the CPU. Each data byte (after the first one) should be written only after a "Tx Data Register Empty" (TDRE) interrupt has occurred, or the BSVR register has been polled indicating this condition. Data read from this register will be the last data byte received from the J1850 bus and should be read only after a "Rx Data Register Full" (RDRF) or a "Received IFR Byte" (RXIFR) interrupt has occurred, or the BSVR register has been polled indicating this condition. To stop a transmission that is already in progress simply stop loading more data into the BDR. This will cause a transmitter underrun error and the BDLC will automatically disable the transmitter on the next non-byte boundary. BARD -- BDLC Analog Roundtrip Delay Register
Bit 7 ATE RESET: 1 6 RXPOL 1 5 0 0 4 0 0 3 BO3 0 2 BO2 1 1 BO1 1 Bit 0 BO0 1
$00FC
Programs the BDLC to compensate for various delays of external transceivers. Read anytime. May be written once in normal modes or written anytime in special mode. ATE -- Analog Transceiver Enable 0 = Select off-chip analog transceiver 1 = Select on-board analog transceiver NOTE This device does not contain an on-board transceiver. The ATE bit should be programmed to a logic zero for proper operation. RXPOL -- Receive Pin Polarity This bit selects the polarity of the incoming signal on the receive pin. 0 = Select inverted polarity, where external transceiver inverts the receive signal. 1 = Select normal/true polarity; true non-inverted signal from J1850 bus, i.e., the external transceiver does not invert the receive signal. BO[3:0] -- BARD Offset These bits are used to compensate for the analog transceiver roundtrip delay. The following table shows the expected transceiver delay with respect to BARD offset values: Table 36 Offset Bit Values and Transceiver Delay
BARD Offset Bits (BO3, BO2, BO1, BO0) 0000 0001 0010 0011 0100 Expected Delay (s) 9 10 11 12 13
MOTOROLA 104
MC68HC912B32 MC68HC912B32TS/D
Table 36 Offset Bit Values and Transceiver Delay
BARD Offset Bits (BO3, BO2, BO1, BO0) 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Expected Delay (s) 14 15 16 17 18 19 20 21 22 23 24
DLCSCR -- Port DLC Control Register
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 BDLCEN 0 1 PUPDLC 0 Bit 0 RDPDLC 0
$00FD
The BDLC port DLC functions as a general-purpose I/O port. BDLC functions takes precedence over the general-purpose port when enabled. Read or write anytime. BDLCEN -- BDLC Enable 0 = Configure BDLC I/O pins as general-purpose I/O pins. BDLC is off. 1 = Configure I/O pins for BDLC function. BDLC is active. PUPDLC -- BDLC Pull-Up Enable 0 = Disconnects internal pull-ups from PORTDLC I/O pins. 1 = Connects internal pull-ups to PORTDLC I/O pins. RDPDLC -- BDLC Reduced Drive 0 = Configure PORTDLC I/O pins for normal drive strength. 1 = Configure PORTDLC I/O pins for reduced drive strength. PORTDLC -- Port DLC Data Register
Bit 7 0 RESET: Alt. Pin Function 0 - 6 Bit 6 - - 5 5 - - 4 4 - - 3 3 - - 2 2 - - 1 1 - DLCTX Bit 0 Bit 0 - DLCRX
$00FE
Holds data to be driven out on port DLC pins or data received from port DLC pins. PORTDLC can be read anytime. When configured as an input, a read will return the pin level. When configured as output, a read will return the latched output data. Writes will not change pin state when the pins are configured for BDLC output. Upon reset pins are configured for general-purpose high impedance inputs.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 105
DDRDLC -- Port DLC Data Direction Register
Bit 7 0 RESET: 0 6 DDDLC6 0 5 DDDLC5 0 4 DDDLC4 0 3 DDDLC3 0 2 DDDLC2 0 1 DDDLC1 0 Bit 0 DDDLC0 0
$00FF
Read and write anytime. DDDLC[6:0] -- Data Direction Port DLC Pin 6 through Pin 0 0 = Configure I/O pin for input only 1 = Configure I/O pin for output 14.5 J1850 Bus Errors The BDLC detects several types of transmit and receive errors which can occur during the transmission of a message onto the J1850 bus. If the BDLC transmits a message containing invalid bits, or framing symbols on non-byte boundaries, then a transmission error has occurred. When a transmission error is detected, the BDLC will immediately cease transmitting. The error condition is reflected in the BSVR register. If the interrupt enable bit (IE) is set, an interrupt request from the BDLC is generated. CRC Error -- A CRC error is detected when the data bytes and CRC byte of a received message are processed, and the CRC calculation result is not equal to $C4. The CRC code should detect any single and 2-bit errors, as well as all 8-bit burst errors, and almost all other types of errors. CRC error flag is set when a CRC error is detected. Symbol Error -- A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the J1850 bus. However, if the BDLC is transmitting when this happens, it may be treated as a loss of arbitration rather than a transmitter error. Symbol invalid or out of range flag is set when a symbol error is detected. Framing Error -- A framing error is detected if an EOD or EOF symbol is detected on a non-byte boundary from the J1850 bus. Symbol invalid or out of range flag is set when a framing error is detected. Bus Fault -- If a bus fault occurs, the response of the BDLC will depend upon the type of bus fault. If the bus is shorted to VBATT, the BDLC will wait for the bus to fall to a passive state before it will attempt to transmit a message. As long as the short remains, the BDLC will never attempt to transmit a message onto the J1850 bus. If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit the message, and then detect a transmission error, since the short to ground would not allow the bus to be driven to the active (dominant) state. The BDLC will abort that transmission and wait for the next CPU command to transmit. In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC will resume normal operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850 bus. BREAK -- Any BDLC transmitting at the time a BREAK is detected will treat the BREAK as if a transmission error had occurred, and halt transmission. If while receiving a message the BDLC detects a BREAK symbol, it will treat the BREAK as a reception error.
MOTOROLA 106
MC68HC912B32 MC68HC912B32TS/D
If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol interrupt will be generated. Reading the BSVR register will clear this interrupt condition. The BDLC will wait for the bus to idle, then wait for SOF. The BDLC cannot transmit a BREAK symbol. It can only receive a BREAK symbol from the J1850 bus. Table 37 BDLC J1850 Bus Error Summary
Error Condition Bus short to VBATT Bus short to ground Invalid symbol: BDLC receives invalid bits (noise) Framing Error CRC Error BDLC receives BREAK symbol BDLC Function The BDLC will not transmit until the bus is idle. Thermal overload will shutdown physical interface. Fault condition is reflected in BSVR as invalid symbol. The BDLC will abort transmission immediately. Invalid symbol interrupt will be generated. Invalid symbol interrupt will be generated. The BDLC will wait for SOF. CRC error interrupt will be generated. The BDLC will wait for SOF. The BDLC will wait for the next valid SOF. Invalid symbol interrupt will be generated.
Invalid Symbol: BDLC sends an Invalid symbol interrupt will be generated. EOD but receives an active symbol The BDLC will wait for SOF.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 107
15 Analog-To-Digital Converter
The ATD is an 8-channel, 8-bit, multiplexed-input successive-approximation analog-to-digital converter, accurate to 1 least significant bit (LSB). It does not require external sample and hold circuits because of the type of charge redistribution technique used. The ATD converter timing is synchronized to the system P clock. The ATD module consists of a 16-word (32-byte) memory-mapped control register block used for control, testing and configuration.
RC DAC ARRAY AND COMPARATOR
VRH VRL
REFERENCE
VDDA SUPPLY VSSA MODE AND TIMING CONTROLS SAR ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 CLOCK SELECT/PRESCALE PORT AD DATA INPUT REGISTER ANALOG MUX AND SAMPLE BUFFER AMP AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0
INTERNAL BUS
HC12 ATD BLOCK
Figure 26 Analog-to-Digital Converter Block Diagram 15.1 Functional Description A single conversion sequence consists of four or eight conversions, depending on the state of the select 8 channel mode (S8CM) bit when ATDCTL5 is written. There are eight basic conversion modes. In the non-scan modes, the SCF bit is set after the sequence of four or eight conversions has been performed and the ATD module halts. In the scan modes, the SCF bit is set after the first sequence of four or eight conversions has been performed, and the ATD module continues to restart the sequence. In both modes, the CCF bit associated with each register is set when that register is loaded with the appropriate conversion result. That flag is cleared automatically when that result register is read. The conversions are started by writing to the control registers. 15.2 ATD Registers ATDCTL0 -- Reserved
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$0060
MOTOROLA 108
MC68HC912B32 MC68HC912B32TS/D
ATDCTL1 -- Reserved
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
$0061
ATDCTL2 -- ATD Control Register 2
Bit 7 ADPU RESET: 0 6 AFFC 0 5 ASWAI 0 4 0 0 3 0 0 2 0 0 1 ASCIE 0 Bit 0 ASCIF 0
$0062
The ATD control register 2 and 3 are used to select the power up mode, interrupt control, and freeze control. Writes to these registers abort any current conversion sequence. Read or write anytime except ASCIF bit, which cannot be written. Bit positions ATDCTL2[4:2] and ATDCTL3[7:2] are unused and always read as zeros. ADPU -- ATD Disable 0 = Disables the ATD, including the analog section for reduction in power consumption. 1 = Allows the ATD to function normally. Software can disable the clock signal to the ATD converter and power down the analog circuits to reduce power consumption. When reset to zero, the ADPU bit aborts any conversion sequence in progress. Because the bias currents to the analog circuits are turned off, the ATD requires a period of recovery time to stabilize the analog circuits after setting the ADPU bit. AFFC -- ATD Fast Flag Clear All 0 = ATD flag clearing operates normally (read the status register before reading the result register to clear the associate CCF bit). 1 = Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register (ATD0-7) will cause the associated CCF flag to clear automatically if it was set at the time. ASWAI -- ATD Stop in Wait Mode 0 = ATD continues to run when the MCU is in wait mode 1 = ATD stops to save power when the MCU is in wait mode ASCIE -- ATD Sequence Complete Interrupt Enable 0 = Disables ATD interrupt 1 = Enables ATD interrupt on sequence complete ASCIF -- ATD Sequence Complete Interrupt Cannot be written in any mode. 0 = No ATD interrupt occurred 1 = ATD sequence complete ATDCTL3 -- ATD Control Register 3
Bit 7 0 RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 FRZ1 0 Bit 0 FRZ0 0
$0063
FRZ1, FRZ0 -- Background Debug (Freeze) Enable (suspend module operation at breakpoint) When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint is encountered. These two bits determine how the ATD will respond when background debug mode becomes active.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 109
Table 38 ATD Response to Background Debug Enable
FRZ1 FRZ0 0 0 1 1 0 1 0 1 ATD Response Continue conversions in active background mode Reserved Finish current conversion, then freeze Freeze when BDM is active
ATDCTL4 -- ATD Control Register 4
Bit 7 0 RESET: 0 6 SMP1 0 5 SMP0 0 4 PRS4 0 3 PRS3 0 2 PRS2 0 1 PRS1 0 Bit 0 PRS0 1
$0064
The ATD control register 4 is used to select the clock source and set up the prescaler. Writes to the ATD control registers initiate a new conversion sequence. If a write occurs while a conversion is in progress, the conversion is aborted and ATD activity halts until a write to ATDCTL5 occurs. SMP1, SMP0 -- Select Sample Time These bits are used to select one of four sample times after the buffered sample and transfer has occurred. Total conversion time depends on initial sample time (two ATD clocks), transfer time (two ATD clocks), final sample time (programmable, refer to Table 39), and resolution time (ten ATD clocks). Table 39 Final Sample Time Selection
SMP1 0 0 1 1 SMP0 0 1 0 1 Final Sample Time 2 ATD clock periods 4 ATD clock periods 8 ATD clock periods 16 ATD clock periods Total 8-Bit Conversion Time 16 ATD clock periods 18 ATD clock periods 22 ATD clock periods 30 ATD clock periods
PRS4, PRS3, PRS2, PRS1, PRS0 -- Select Divide-By Factor for ATD P-Clock Prescaler. The binary value written to these bits (1 to 31) selects the divide-by factor for the modulo counter-based prescaler. The P clock is divided by this value plus one and then fed into a /2 circuit to generate the ATD module clock. The divide-by-two circuit insures symmetry of the output clock signal. Clearing these bits causes the prescale value to default to one which results in a /2 prescale factor. This signal is then fed into the /2 logic. The reset state divides the P clock by a total of four and is appropriate for nominal operation between 2 MHz and 8 MHz bus rate. Table 40 shows the divide-by operation and the appropriate range of system clock frequencies.
MOTOROLA 110
MC68HC912B32 MC68HC912B32TS/D
Table 40 Clock Prescaler Values
Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01xxx 1xxxx Total Divisor Max P Clock1 4 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz Do Not Use Min P Clock2 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz
/2 /4 /6 /8 /10 /12 /14 /16
NOTES: 1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become maximum conversion rate that can be used on this ATD module. 2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become minimum conversion rate that this ATD can perform.
ATDCTL5 -- ATD Control Register 5
Bit 7 0 RESET: 0 6 S8CM 0 5 SCAN 0 4 MULT 0 3 CD 0 2 CC 0 1 CB 0 Bit 0 CA 0
$0065
The ATD control register 5 is used to select the conversion modes, the conversion channel(s), and initiate conversions. Read or write anytime. Writes to the ATD control registers initiate a new conversion sequence. If a conversion sequence is in progress when a write occurs, that sequence is aborted and the SCF and CCF bits are reset. S8CM -- Select 8 Channel Mode 0 = Conversion sequence consists of four conversions 1 = Conversion sequence consists of eight conversions SCAN -- Enable Continuous Channel Scan 0 = Single conversion sequence 1 = Continuous conversion sequences (scan mode) When a conversion sequence is initiated by a write to the ATDCTL register, the user has a choice of performing a sequence of four (or eight, depending on the S8CM bit) conversions or continuously performing four (or eight) conversion sequences. MULT -- Enable Multichannel Conversion 0 = ATD sequencer runs all four or eight conversions on a single input channel selected via the CD, CC, CB, and CA bits. 1 = ATD sequencer runs each of the four or eight conversions on sequential channels in a specific group. Refer to Table 41. CD, CC, CB, and CA -- Channel Select for Conversion
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 111
Table 41 Multichannel Mode Result Register Assignment
S8CM CD CC CB 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel Signal AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH + VRL)/2 TEST/Reserved AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH + VRL)/2 TEST/Reserved Result in ADRx if MULT = 1 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7
Shaded bits are "don't care" if MULT = 1 and the entire block of four or eight channels make up a conversion sequence. When MULT = 0, all four bits (CD, CC, CB, and CA) must be specified and a conversion sequence consists of four or eight consecutive conversions of the single specified channel.
MOTOROLA 112
MC68HC912B32 MC68HC912B32TS/D
ATDSTAT -- ATD Status Register
Bit 7 SCF RESET: 0 6 0 0 5 0 0 4 0 0 3 0 0 2 CC2 0 1 CC1 0 Bit 0 CC0 0
$0066
ATDSTAT -- ATD Status Register
Bit 7 CCF7 RESET: 0 6 CCF6 0 5 CCF5 0 4 CCF4 0 3 CCF3 0 2 CCF2 0 1 CCF1 0 Bit 0 CCF0 0
$0067
The ATD status registers contain the flags indicating the completion of ATD conversions. Normally, it is read-only. In special mode, the SCF bit and the CCF bits may also be written. SCF -- Sequence Complete Flag This bit is set at the end of the conversion sequence when in the single conversion sequence mode (SCAN = 0 in ATDCTL5) and is set at the end of the first conversion sequence when in the continuous conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is cleared when a write is performed to ATDCTL5 to initiate a new conversion sequence. When AFFC = 1, SCF is cleared after the first result register is read. CC[2:0] -- Conversion Counter for Current Sequence of Four or Eight Conversions This 3-bit value reflects the contents of the conversion counter pointer in a four or eight count sequence. This value also reflects which result register will be written next, indicating which channel is currently being converted. CCF[7:0] -- Conversion Complete Flags Each of these bits are associated with an individual ATD result register. For each register, this bit is set at the end of conversion for the associated ATD channel and remains set until that ATD result register is read. It is cleared at that time if AFFC bit is set, regardless of whether a status register read has been performed (i.e., a status register read is not a pre-qualifier for the clearing mechanism when AFFC = 1). Otherwise the status register must be read to clear the flag. ATDTSTH -- ATD Test Register
Bit 7 SAR9 RESET: 0 6 SAR8 0 5 SAR7 0 4 SAR6 0 3 SAR5 0 2 SAR4 0 1 SAR3 0 Bit 0 SAR2 0
$0068
ATDTSTL -- ATD Test Register
Bit 7 SAR1 RESET: 0 6 SAR0 0 5 RST 0 4 TSTOUT 0 3 TST3 0 2 TST2 0 1 TST1 0 Bit 0 TST0 0
$0069
The test registers control various special modes which are used during manufacturing. The test register can be read or written only in the special modes. In the normal modes, reads of the test register return zero and writes have no effect. SAR[9:0] -- SAR Data Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value written. Bits SAR[9:2] reflect the eight SAR bits used during the resolution process for an 8-bit result. SAR1 and SAR0 are reserved to allow future derivatives to increase ATD resolution to ten bits.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 113
RST -- Module Reset Bit When set, this bit causes all registers and activity in the module to assume the same state as out of power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to remain enabled). TSTOUT -- Multiplex Output of TST[3:0] (Factory Use) TST[3:0] -- Test Bits 3 to 0 (Reserved) Selects one of 16 reserved factory testing modes. PORTAD -- Port AD Data Input Register
Bit 7 PAD7 RESET: - 6 PAD6 - 5 PAD5 - 4 PAD4 - 3 PAD3 - 2 PAD2 - 1 PAD1 - Bit 0 PAD0 -
$006F
PAD[7:0] -- Port AD Data Input Bits After reset these bits reflect the state of the input pins. May be used for general-purpose digital input. When the software reads PORTAD, it obtains the digital levels that appear on the corresponding port AD pins. Pins with signals not meeting VIL or VIH specifications will have an indeterminate value. Writes to this register have no meaning at any time. ADR0H -- ATD Converter Result Register 0 ADR1H -- ATD Converter Result Register 1 ADR2H -- ATD Converter Result Register 2 ADR3H -- ATD Converter Result Register 3 ADR4H -- ATD Converter Result Register 4 ADR5H -- ATD Converter Result Register 5 ADR6H -- ATD Converter Result Register 6 ADR7H -- ATD Converter Result Register 7
$007x Bit 7 Bit 7 RESET: - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - Bit 0 Bit 0 -
$0070 $0072 $0074 $0076 $0078 $007A $007C $007E
ADRxH[7:0] -- ATD Conversion Result The reset condition for these registers is undefined. These bits contain the left justified, unsigned result from the ATD conversion. The channel from which this result was obtained is dependent on the conversion mode selected. These registers are always read-only in normal mode. 15.3 ATD Mode Operation STOP -- causes all clocks to halt (if the S bit in the CCR is zero). The system is placed in a minimumpower standby mode. This aborts any conversion sequence in progress. During STOP recovery, the ATD must delay for the STOP recovery time (tSR) before initiating a new ATD conversion sequence. WAIT -- ATD conversion continues unless AWAI bit in ATDCTL2 register is set. BDM -- Debug options available as set in register ATDCTL3. USER -- ATD continues running unless ADPU is cleared. ADPU -- ATD operations are stopped if ADPU = 0, but registers are accessible.
MOTOROLA 114
MC68HC912B32 MC68HC912B32TS/D
16 Development Support
Development support involves complex interactions between MC68HC912B32 resources and external development systems. The following section concerns instruction queue and queue tracking signals, background debug mode, and instruction tagging. 16.1 Instruction Queue The CPU12 instruction queue provides at least three bytes of program information to the CPU when instruction execution begins. The CPU12 always completely finishes executing an instruction before beginning to execute the next instruction. Status signals IPIPE[1:0] provide information about data movement in the queue and indicate when the CPU begins to execute instructions. This makes it possible to monitor CPU activity on a cycle-by-cycle basis for debugging. Information available on the IPIPE[1:0] pins is time multiplexed. External circuitry can latch data movement information on rising edges of the E-clock signal; execution start information can be latched on falling edges. Table 42 shows the meaning of data on the pins. Table 42 IPIPE Decoding
Data Movement -- IPIPE[1:0] Captured at Rising Edge of E Clock1 IPIPE[1:0] 0:0 0:1 1:0 1:1 IPIPE[1:0] 0:0 0:1 1:0 1:1 Mnemonic -- LAT ALD ALL Mnemonic -- INT SEV SOD No Start Start Interrupt Sequence Start Even Instruction Start Odd Instruction No Movement Latch Data From Bus Advance Queue and Load From Bus Advance Queue and Load From Latch Meaning Meaning
Execution Start -- IPIPE[1:0] Captured at Falling Edge of E Clock2
NOTES: 1. Refers to data that was on the bus at the previous E falling edge. 2. Refers to bus cycle starting at this E falling edge.
Program information is fetched a few cycles before it is used by the CPU. In order to monitor cycle-bycycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue. Internally the MCU only needs to buffer the data from program fetches. For system debug it is necessary to keep the data and its associated address in the reconstructed instruction queue. The raw signals required for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and status signals IPIPE[1:0]. The instruction queue consists of two 16-bit queue stages and a holding latch on the input of the first stage. To advance the queue means to move the word in the first stage to the second stage and move the word from either the holding latch or the data bus input buffer into the first stage. To start even (or odd) instruction means to execute the opcode in the high-order (or low-order) byte of the second stage of the instruction queue. 16.2 Background Debug Mode Background debug mode (BDM) is used for system development, in-circuit testing, field testing, and programming. BDM is implemented in on-chip hardware and provides a full set of debug options. Because BDM control logic does not reside in the CPU, BDM hardware commands can be executed while the CPU is operating normally. The control logic generally uses CPU dead cycles to execute these
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 115
commands, but can steal cycles from the CPU when necessary. Other BDM commands are firmware based, and require the CPU to be in active background mode for execution. While BDM is active, the CPU executes a firmware program located in a small on-chip ROM that is available in the standard 64Kbyte memory map only while BDM is active. The BDM control logic communicates with an external host development system serially, via the BKGD pin. This single-wire approach minimizes the number of pins needed for development support. 16.2.1 Enabling BDM Firmware Commands BDM is available in all operating modes, but must be made active before firmware commands can be executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single wire interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to map BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background mode. After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by the BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firmware has been enabled causes the MCU to resume normal instruction execution after a brief delay. BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND command, but tags activate BDM before a tagged instruction is executed. In special single-chip mode, background operation is enabled and active immediately out of reset. This active case replaces the M68HC11 boot function, and allows programming a system with blank memory. While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The BDM control logic uses these registers which can be read anytime by BDM logic, not user programs. Refer to 16.2.4 BDM Registers for detailed descriptions. Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function during BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once normal program flow is continued, the timer counter is re-enabled to simulate real-time operations. 16.2.2 BDM Serial Interface The BDM serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 E-clock cycles per bit (nominal speed). The interface times out if 256 E-clock cycles occur between falling edges from the host. The hardware clears the command register when a time-out occurs. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to MCU clocks but asynchronous to the external host. The internal clock signal is shown for reference in counting cycles. Figure 27 shows an external host transmitting a logic one or zero to the BKGD pin of a target MC68HC912B32 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Nine target E cycles later, the target senses the bit level on the BKGD pin. Typically the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Since the target does not drive the BKGD pin during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions.
MOTOROLA 116
MC68HC912B32 MC68HC912B32TS/D
E CLOCK (TARGET MCU)
HOST TRANSMIT 1
HOST TRANSMIT 0 PERCEIVED START OF BIT TIME SYNCHRONIZATION UNCERTAINTY
TARGET SENSES BIT 9 CYCLES EARLIEST START OF NEXT BIT
HC12A4 BDM HOST TO TARGET TIM
Figure 27 BDM Host to Target Serial Bit Timing
E CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME BKGD PIN HIGH-IMPEDANCE
HIGH-IMPEDANCE
R-C RISE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HC12A4 BDM TARGET TO HOST TIM 1
HOST SAMPLES BKGD PIN
Figure 28 BDM Target to Host Serial Bit Timing (Logic 1) Figure 28 shows the host receiving a logic one from the target MC68HC912B32 MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target E cycles). The host must release the low drive before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about ten cycles after it started the bit time.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 117
E CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN
HIGH-IMPEDANCE SPEEDUP PULSE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HC12A4 BDM TARGET TO HOST TIM 0
HOST SAMPLES BKGD PIN
Figure 29 BDM Target to Host Serial Bit Timing (Logic 0) Figure 29 shows the host receiving a logic zero from the target MC68HC912B32 MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MC68HC912B32 finishes it. Since the target wants the host to receive a logic zero, it drives the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about ten cycles after starting the bit time. 16.2.3 BDM Commands All BDM command opcodes are eight bits long, and can be followed by an address and/or data, as indicated by the instruction. These commands do not require the CPU to be in active BDM mode for execution. The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data read commands, the host must insert this delay between sending the address and attempting to read the data. BDM logic retains control of the internal buses until a read or write is completed. If an operation can be completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation requires multiple cycles, CPU clocks are frozen until the operation is complete.
MOTOROLA 118
MC68HC912B32 MC68HC912B32TS/D
Table 43 BDM Commands Implemented in Hardware
Command BACKGROUND READ_BD_BYTE Opcode (Hex) 90 E4 Data None 16-bit address 16-bit data out FF01, 0000 0000 (out) STATUS1 E4 FF01, 1000 0000 (out) FF01, 1100 0000 (out) READ_BD_WORD EC 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data in Description Enter background mode (if firmware enabled). Read from memory with BDM in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. READ_BD_BYTE $FF01. Running user code (BGND instruction is not allowed). READ_BD_BYTE $FF01. BGND instruction is allowed. READ_BD_BYTE $FF01. Background mode active (waiting for single wire serial command). Read from memory with BDM in map (may steal cycles if external access) must be aligned access. Read from memory with BDM out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. Read from memory with BDM out of map (may steal cycles if external access) must be aligned access. Write to memory with BDM in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. Write byte $FF01, set the ENBDM bit. This allows execution of commands which are implemented in firmware. Typically, read STATUS, OR in the MSB, write the result back to STATUS. Write to memory with BDM in map (may steal cycles if external access) must be aligned access. Write to memory with BDM out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. Write to memory with BDM out of map (may steal cycles if external access) must be aligned access.
READ_BYTE
E0
READ_WORD
E8
WRITE_BD_BYTE
C4
ENABLE_ FIRMWARE2
C4
FF01, 1xxx xxxx(in) 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in
WRITE_BD_WORD
CC
WRITE_BYTE
C0
WRITE_WORD
C8
NOTES: 1. STATUS command is a specific case of the READ_BD_BYTE command. 2. ENABLE_FIRMWARE and ENTER_TAG_MODE are specific cases of the WRITE_BD_BYTE command.
The CPU must be in background mode to execute commands that are implemented in the BDM ROM. The BDM ROM is located at $FF20 to $FFFF while BDM is active. There are also seven bytes of BDM registers which are located at $FF00 to $FF06 while BDM is active. The CPU executes code from this ROM to perform the requested operation. These commands are shown in Table 44.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 119
Table 44 BDM Firmware Commands
Command READ_NEXT READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO TRACE1 TAGGO Opcode (Hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 10 18 Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in None None None Description X = X + 2; Read next word pointed-to by X Read program counter Read D accumulator Read X index register Read Y index register Read stack pointer X = X + 2; Write next word pointed-to by X Write program counter Write D accumulator Write X index register Write Y index register Write stack pointer Go to user program Execute one user instruction then return to BDM Enable tagging and go to user program
16.2.4 BDM Registers Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active. The registers can be accessed with the hardware READ_BD and WRITE_BD commands, but must not be written during BDM operation. Most users will only be interested in the STATUS register at $FF01; other registers are only for use by BDM firmware and logic. The instruction register is discussed for two conditions: when a hardware command is executed and when a firmware command is executed. INSTRUCTION -- BDM Instruction Register (hardware command bit explanation)
Bit 7 H/F 6 DATA 5 R/W 4 BKGND 3 W/B 2 BD/U 1 0
(BDM) $FF00
Bit 0 0
The bits in the BDM instruction register have the following meanings when a hardware command is executed. H/F -- Hardware/Firmware Flag 0 = Firmware instruction 1 = Hardware instruction DATA -- Data Flag 0 = No data 1 = Data included in command R/W -- Read/Write Flag 0 = Write 1 = Read BKGND -- Hardware request to enter active background mode 0 = Not a hardware background command 1 = Hardware background command (INSTRUCTION = $90)
MOTOROLA 120
MC68HC912B32 MC68HC912B32TS/D
W/B -- Word/Byte Transfer Flag 0 = Byte transfer 1 = Word transfer BD/U -- BDM Map/User Map Flag Indicates whether BDM registers and ROM are mapped to addresses $FF00 to $FFFF in the standard 64-Kbyte address space. Used only by hardware read/write commands. 0 = BDM resources not in map 1 = BDM resources in map INSTRUCTION -- BDM Instruction Register (firmware command bit explanation)
Bit 7 H/F 6 DATA 5 R/W 4 TTAGO 3 2 1 REGN
(BDM) $FF00
Bit 0
The bits in the BDM instruction register have the following meanings when a firmware command is executed. H/F -- Hardware/Firmware Flag 0 = Firmware control logic 1 = Hardware control logic DATA -- Data Flag 0 = No data 1 = Data included in command R/W -- Read/Write Flag 0 = Write 1 = Read TTAGO -- Trace, Tag, Go Field Table 45 TTAGO Decoding
TTAGO Value 00 01 10 11 Instruction -- GO TRACE1 TAGGO
REGN -- Register/Next Field Indicates which register is being affected by a command. In the case of a READ_NEXT or WRITE_NEXT command, index register X is pre-incremented by two and the word pointed to by X is then read or written. Table 46 REGN Decoding
REGN Value 000 001 010 011 100 101 110 111 Instruction -- -- READ/WRITE NEXT PC D X Y SP
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 121
STATUS -- BDM Status Register
Bit 7 ENBDM RESET: 0 6 BDMACT 0 5 ENTAG 0 4 SDV 1 3 TRACE 0 2 0 0 1 0 0
(BDM) $FF01
Bit 0 0 0
This register can be read or written by BDM commands or firmware. ENBDM -- Enable BDM (permit active background debug mode) 0 = BDM cannot be made active (hardware commands still allowed) 1 = BDM can be made active to allow firmware commands BDMACT -- Background Mode Active Status 0 = BDM not active 1 = BDM active and waiting for serial commands ENTAG -- Instruction Tagging Enable Set by the TAGGO instruction and cleared when BDM is entered. 0 = Tagging not enabled, or BDM active 1 = Tagging active (BDM cannot process serial commands while tagging is active.) SDV -- Shifter Data Valid Shows that valid data is in the serial interface shift register. Used by firmware-based instructions. 0 = No valid data 1 = Valid Data TRACE -- Asserted by the TRACE1 instruction SHIFTER -- BDM Shift Register
Bit 15 S15 14 S14 13 S13 12 S12 11 S11 10 S10 9 S9
(BDM) $FF02, $FF03
Bit 8 S8
Bit 7 S7
6 S6
5 S5
4 S4
3 S3
2 S2
1 S1
Bit 0 S0
This 16-bit register contains data being received or transmitted via the serial interface. ADDRESS -- BDM Address Register
Bit 15 A15 14 A14 13 A13 12 A12 11 A11 10 A10 9 A9
(BDM) $FF04, $FF05
Bit 8 A8
Bit 7 A7
6 A6
5 A5
4 A4
3 A3
2 A2
1 A1
Bit 0 A0
This 16-bit register is temporary storage for BDM hardware and firmware commands. CCRSAV -- BDM CCR Holding Register
Bit 7 CCR7 6 CCR6 5 CCR5 4 CCR4 3 CCR3 2 CCR2 1 CCR1
(BDM) $FF06
Bit 0 CCR0
This register preserves the content of the CPU12 CCR while BDM is active.
MOTOROLA 122
MC68HC912B32 MC68HC912B32TS/D
16.3 Breakpoints Hardware breakpoints are used to debug software on the MC68HC912B32 by comparing actual address and data values to predetermined data in setup registers. A successful comparison will place the CPU in background debug mode (BDM) or initiate a software interrupt (SWI). Breakpoint features designed into the MC68HC912B32 include: * Mode selection for BDM or SWI generation * Program fetch tagging for cycle of execution breakpoint * Second address compare in dual address modes * Range compare by disable of low byte address * Data compare in full feature mode for non-tagged breakpoint * Byte masking for high/low byte data compares * R/W compare for non-tagged compares * Tag inhibit on BDM TRACE 16.3.1 Breakpoint Modes Three modes of operation determine the type of breakpoint in effect. * Dual address-only breakpoints, each of which will cause a software interrupt (SWI) * Single full-feature breakpoint which will cause the part to enter background debug mode (BDM) * Dual address-only breakpoints, each of which will cause the part to enter BDM Breakpoints will not occur when BDM is active. 16.3.1.1 SWI Dual Address Mode In this mode, dual address-only breakpoints can be set, each of which cause a software interrupt. This is the only breakpoint mode which can force the CPU to execute a SWI. Program fetch tagging is the default in this mode; data breakpoints are not possible. In the dual mode each address breakpoint is affected by the BKPM bit and the BKALE bit. The BKxRW and BKxRWE bits are ignored. In dual address mode the BKDBE becomes an enable for the second address breakpoint. The BKSZ8 bit will have no effect when in a dual address mode. 16.3.1.2 BDM Full Breakpoint Mode A single full feature breakpoint which causes the part to enter background debug mode. BDM mode may be entered by a breakpoint only if an internal signal from the BDM indicates background debug mode is enabled. * Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU is executing out of the BDM ROM. * BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. This is important because even if the ENABLE bit in the BDM is negated the CPU actually does execute the BDM ROM code. It checks the ENABLE and returns if not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. * There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. 16.3.1.3 BDM Dual Address Mode Dual address-only breakpoints, each of which cause the part to enter background debug mode. In the dual mode each address breakpoint is affected, consistent across modes, by the BKPM bit, the BKALE bit, and the BKxRW and BKxRWE bits. In dual address mode the BKDBE becomes an enable for the second address breakpoint. The BKSZ8 bit will have no effect when in a dual address mode. BDM mode may be entered by a breakpoint only if an internal signal from the BDM indicates background debug mode is enabled. * BKDBE will be used as an enable for the second address only breakpoint.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 123
* Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU is executing out of the BDM ROM. * BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. This is important because even if the ENABLE bit in the BDM is negated the CPU actually does execute the BDM ROM code. It checks the ENABLE and returns if not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. 16.3.2 Registers Breakpoint operation consists of comparing data in the breakpoint address registers (BRKAH/BRKAL) to the address bus and comparing data in the breakpoint data registers (BRKDH/BRKDL) to the data bus. The breakpoint data registers can also be compared to the address bus. The scope of comparison can be expanded by ignoring the least significant byte of address or data matches. The scope of comparison can be limited to program data only by setting the BKPM bit in breakpoint control register 0. To trace program flow, setting the BKPM bit causes address comparison of program data only. Control bits are also available that allow checking read/write matches. BRKCT0 -- Breakpoint Control Register 0
Bit 7 BKEN1 RESET: 0 6 BKEN0 0 5 BKPM 0 4 0 0 3 BK1ALE 0 2 BK0ALE 0 1 0 0 Bit 0 0 0
$0020
Read and write anytime. This register is used to control the breakpoint logic. BKEN1, BKEN0 -- Breakpoint Mode Enable Table 47 Breakpoint Mode Control
BKEN1 BKEN0 Mode Selected 0 0 Breakpoints Off 0 1 SWI -- Dual Address Mode 1 0 BDM -- Full Breakpoint Mode 1 1 BDM -- Dual Address Mode BRKAH/L Usage -- Address Match Address Match Address Match BRKDH/L Usage -- Address Match Data Match Address Match R/W -- No Yes Yes Range -- Yes Yes Yes
BKPM -- Break on Program Addresses This bit controls whether the breakpoint will cause a break on a match (next instruction boundary) or on a match that will be an executable opcode. Data and unexecuted opcodes cannot cause a break if this bit is set. This bit has no meaning in SWI dual address mode. The SWI mode only performs program breakpoints. 0 = On match, break at the next instruction boundary 1 = On match, break if the match is an instruction that will be executed. This uses tagging as its breakpoint mechanism. BK1ALE -- Breakpoint 1 Range Control Only valid in dual address mode. 0 = BRKDL will not be used to compare to the address bus. 1 = BRKDL will be used to compare to the address bus. BK0ALE -- Breakpoint 0 Range Control Valid in all modes. 0 = BRKAL will not be used to compare to the address bus. 1 = BRKAL will be used to compare to the address bus.
MOTOROLA 124
MC68HC912B32 MC68HC912B32TS/D
Table 48 Breakpoint Address Range Control
BK1ALE - - 0 1 BK0ALE 0 1 - - Address Range Selected Upper 8-bit address only for full mode or dual mode BKP0 Full 16-bit address for full mode or dual mode BKP0 Upper 8-bit address only for dual mode BKP1 Full 16-bit address for dual mode BKP1
BRKCT1 -- Breakpoint Control Register 1
Bit 7 0 RESET: 0 6 BKDBE 0 5 BKMBH 0 4 BKMBL 0 3 BK1RWE 0 2 BK1RW 0 1 BK0RWE 0 Bit 0 BK0RW 0
$0021
This register is read/write in all modes. BKDBE -- Enable Data Bus Enables comparing of address or data bus values using the BRKDH/L registers. 0 = The BRKDH/L registers are not used in any comparison 1 = The BRKDH/L registers are used to compare address or data (depending upon the mode selections BKEN1,0) BKMBH -- Breakpoint Mask High Disables the comparing of the high byte of data when in full breakpoint mode. Used in conjunction with the BKDBE bit (which should be set) 0 = High byte of data bus (bits 15:8) are compared to BRKDH 1 = High byte is not used to in comparisons BKMBL -- Breakpoint Mask Low Disables the matching of the low byte of data when in full breakpoint mode. Used in conjunction with the BKDBE bit (which should be set) 0 = Low byte of data bus (bits 7:0) are compared to BRKDL 1 = Low byte is not used to in comparisons. BK1RWE -- R/W Compare Enable Enables the comparison of the R/W signal to further specify what causes a match. This bit is NOT useful in program breakpoints or in full breakpoint mode. This bit is used in conjunction with a second address in dual address mode when BKDBE=1. 0 = R/W is not used in comparisons 1 = R/W is used in comparisons BK1RW -- R/W Compare Value When BK1RWE = 1, this bit determines the type of bus cycle to match. 0 = A write cycle will be matched 1 = A read cycle will be matched BK0RWE -- R/W Compare Enable Enables the comparison of the R/W signal to further specify what causes a match. This bit is not useful in program breakpoints. 0 = R/W is not used in the comparisons 1 = R/W is used in comparisons BK0RW -- R/W Compare Value When BK0RWE = 1, this bit determines the type of bus cycle to match on. 0 = Write cycle will be matched 1 = Read cycle will be matched
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 125
Table 49 Breakpoint Read/Write Control
BK1RWE - - - 0 1 1 BK1RW - - - X 0 1 BK0RWE 0 1 1 - - - BK0RW X 0 1 - - - Read/Write Selected R/W is don't care for full mode or dual mode BKP0 R/W is write for full mode or dual mode BKP0 R/W is read for full mode or dual mode BKP0 R/W is don't care for dual mode BKP1 R/W is write for dual mode BKP1 R/W is read for dual mode BKP1
BRKAH -- Breakpoint Address Register, High Byte
Bit 7 Bit 15 RESET: 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0
$0022
These bits are used to compare against the most significant byte of the address bus. BRKAL -- Breakpoint Address Register, Low Byte
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0023
These bits are used to compare against the least significant byte of the address bus. These bits may be excluded from being used in the match if BK0ALE = 0. BRKDH -- Breakpoint Data Register, High Byte
Bit 7 Bit 15 RESET: 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0
$0024
These bits are compared to the most significant byte of the data bus or the most significant byte of the address bus in dual address modes. BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the breakpoint comparison. BRKDL -- Breakpoint Data Register, Low Byte
Bit 7 Bit 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
$0025
These bits are compared to the least significant byte of the data bus or the least significant byte of the address bus in dual address modes. BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be used in the breakpoint comparison.
MOTOROLA 126
MC68HC912B32 MC68HC912B32TS/D
16.4 Instruction Tagging The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real time or from trace history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction, because execution has already begun by the time an operation is visible outside the MCU. A separate instruction tagging mechanism is provided for this purpose. Executing the BDM TAGGO command configures two MCU pins for tagging. Tagging information is latched on the falling edge of ECLK along with program information as it is fetched. Tagging is allowed in all modes. Tagging is disabled when BDM becomes active and BDM serial commands cannot be processed while tagging is active. TAGHI is a shared function of the BKGD pin. TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4 cycle before and after the rising edge of the E clock, this pin is the LSTRB driven output. TAGLO and TAGHI inputs are captured at the falling edge of the E clock. A logic zero on TAGHI and/or TAGLO marks (tags) the instruction on the high and/or low byte of the program word that was on the data bus at the same falling edge of the E clock. The tag follows the information in the queue as the queue is advanced. When a tagged instruction reaches the head of the queue, the CPU enters active background debugging mode rather than executing the instruction. This is the mechanism by which a development system initiates hardware breakpoints.
MC68HC912B32 MC68HC912B32TS/D
MOTOROLA 127
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MCUinit, MCUasm, MCUdebug, and RTEK are trademarks of Motorola, Inc. M O T O R O L A and ! are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver Colorado 80217. 1-800-441-2447, (303) 675-2140 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Mfax is a trademark of Motorola, Inc.
M
MC68HC912B32TS/D

▲Up To Search▲

Price & Availability of MC68HC912B32CFU8

	To Download MC68HC912B32CFU8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .